This work studies the self-heating (SH) effect in ultra-thin body ultra-thin buried oxide (UTBB) FDSOI MOSFETs at cryogenic temperatures down to 77 K. S-parameter measurements in a wide frequency range, with the so-called RF technique, are employed to assess SH parameters and related variation of analog figures of merit (FoMs) at different temperatures. Contrary to the expectations, the effect of self-heating on analog FoMs is slightly weaker at cryogenic temperatures with respect to room-temperature case. The extracted thermal resistance and channel temperature rise at 300 K and 77 K in short-channel devices are of the same order of magnitude. The observed increase in SH characteristic frequency with temperature reduction emphasizes the advantage of the RF technique for the fair analysis of SH-related features in advanced technologies at cryogenic temperatures.

This paper presents detailed RF characterization of 28-nm FDSOI nMOSFETs at cryogenic temperatures down to 77 K. Two main RF figures of merit (FoM), i.e., current gain cutoff frequency (f(T)) and maximum oscillation frequency (f(max)), as well as elements of small-signal equivalent circuit are extracted from the measured S-parameters. Increases of f(T) and f(max) by about 85 GHz and about 30 GHz, respectively, are demonstrated at 77 K. The observed behavior of RF FoMs versus temperature is discussed in terms of small-signal equivalent circuit elements, both intrinsic and extrinsic (parasitics). This paper suggests 28-nm FDSOI as a good candidate for future cryogenic applications.

This work studies, for the first time to the authors’ best knowledge, the self-heating (SH) effect in ultra-thin body ultra-thin BOX (UTBB) FDSOI MOSFETs at cryogenic temperatures down to 77 K. S-parameter measurements in a wide frequency range, with the so-called RF technique, is employed to assess SH parameters and related degradation of analog figures of merit (FoMs) at different temperatures. Contrary to the expectations, the effect of self-heating on analog FoMs is slightly weaker at cryogenic temperatures with respect to room-temperature case. The extracted thermal resistance and channel temperature rise at 300 K and 77 K are of the same order of magnitude. The observed increase in SH characteristic frequency with temperature reduction emphasizes the advantage of the RF technique for the fair analysis of SH-related features in advanced technologies at cryogenic temperatures.

This work presents a detailed characterization of 28 nm FDSOI CMOS process at cryogenic temperatures. Electrostatic, Analog and RF Figures of Merit (FoM) are studied. At liquid nitrogen temperatures, 30% to 200% enhancement of drain current, Id, and maximum transconductance, gm_max, values are demonstrated. Current gain cutoff frequency, fT, increase by about 85 GHz is shown. Temperature behavior of analog and RF FoMs is discussed in terms of mobility and series resistance effect. This study suggests 28 nm FDSOI as a good contender for future read-out electronics operated at cryogenic temperatures (as e.g. around qubits or in space).

This work presents a detailed characterization of 28 nm FDSOI CMOS process at cryogenic temperatures. Electrostatic, Analog and RF Figures of Merit (FoM) are studied for the first time to our best knowledge. At cryogenic temperatures, 20-70% enhancement of drain current, Id, and maximum transconductance, gm_max, values as well as up to 100 GHz increase of cut-off frequency, fT, are demonstrated. Temperature behavior of analog and RF FoMs is discussed in terms of mobility and series resistance effect. This first study suggests 28FDSOI as a good contender for future read-out electronics around qubits.

This work presents, for the first time to our best knowledge, RF characterization of 28 nm FDSOI CMOS process at cryogenic temperatures including extraction of parasitic elements of small-signal equivalent circuit and two main RF Figures of Merit (FoM), i.e. current cutoff frequency (fT) and maximum oscillation frequency (fmax). Increases of fT and fmax by about 85 GHz and 30 GHz, respectively, are demonstrated at cryogenic temperatures. The observed behavior of RF FoMs versus temperature is analyzed in terms of small-signal equivalent circuit elements. This study suggests 28 nm FDSOI as a good candidate for future cryogenic applications.

This work investigates, for the first time to our best knowledge, non-linearities in Fully-depleted Silicon-on-Insulator (FDSOI) MOSFETs and compares them with bulk counterparts. 1 st , 2 nd and 3 rd order derivatives of current-voltage I–V characteristics, followed by Harmonic Distortions of 2 nd and 3 rd order (HD 2 and HD 3 ) were extracted based on DC measurements and simulations. Design window (i.e. bias and current conditions) with strongly reduced non-linearity in FDSOI device with respect to the bulk counterpart was identified and reasons of this reduction are discussed. Application of the back-gate bias in FDSOI MOSFET was shown to allow for further improvement of non-linearity.

Effective work function and equivalent oxide thickness are fundamental parameters for technology optimization. In this work, a comprehensive study is done on a large set of FDSOI devices. The extraction of the gate stack parameters is carried out by fitting experimental CV characteristics to quantum simulation, based on self-consistent solution of one dimensional Poisson and Schrodinger equations. A reliable methodology for gate stack parameters is proposed and validated. This study identifies the process modules that impact directly the effective work function from those that only affect the device threshold voltage, due to the device architecture. Moreover, the relative impacts of various process modules on channel thickness and gate oxide thickness are evidenced.

The introduction of strained channel is mandatory to achieve high performance in Ultra-Thin-Body and Buried-Oxide Fully-Depleted-Silicon-On-Insulator (UTBB FDSOI) technology. Especially, compressive SiGe channel has been demonstrated to enhance hole mobility and therefore pMOSFETs drive currents. At the same time, the performance gain induced by this mechanical stressor comes along with layouts effects. In this study, we characterize experimentally the impact of the active region dimensions and shape on the threshold voltage and linear drain current of SiGe channel pMOSFETs directly on insulator fabricated for the 14nm technology node. The pMOS threshold voltage increases by 105mV for a gate-to-STI distance of 80nm compared to 980nm while IODLIN decreases by 51%. An analytical model is proposed to reproduce the layout dependences. The model is based on the stress profile, taking into account both the stress from the SiGe channel and from SiGe source/drain. It reproduces the experimental data with a good accuracy in the cases of symmetric and asymmetric layouts, provided a typical relaxation length of 112nm is used. Finally, a special attention is paid on multifinger transistors, since they are widely used in standard cells designs.

This work demonstrates that the back-gate terminal of a 28nm FDSOI MOSFET can be used up to several tens of GHz for signal processing. Furthermore, the dependence of the main RF figures-of-merit on the back gate bias are experimentally extracted using a 3-port characterization in the frequency range of 10 MHz – 26.5 GHz. We propose a small-signal equivalent circuit constructed based on 3-port measurements allowing for more complete extraction of parasitic elements comparing to the 2-ports one. The effect of back-gate bias on cut-off frequencies is demonstrated and explained in terms of its influence on the relevant parasitic elements.

The Drain Induced Barrier Lowering (DIBL) behavior in Ultra-Thin Body and Buried oxide (UTBB) transistors is investigated in details in the temperature range up to 150°C, for the first time to the best of our knowledge. The analysis is based on experimental data, physical device simulation, compact model (SPICE) simulation and previously published models. Contrary to MASTAR prediction, experiments reveal DIBL increase with temperature. Physical device simulations of different thin-film fully-depleted (FD) devices outline the generality of such behavior. SPICE simulations, with UTSOI DK2.4 model, only partially adhere to experimental trends. Several analytic models available in the literature are assessed for DIBL vs. temperature prediction. Although being the closest to experiments, Fasarakis’ model overestimates DIBL(T) dependence for shortest devices and underestimates it for upsized gate lengths frequently used in ultra-low-voltage (ULV) applications. This model is improved in our work, by introducing a temperature-dependent inversion charge at threshold. The improved model shows very good agreement with experimental data, with high gain in precision for the gate lengths under test.

This work investigates experimentally the non-linearities of FDSOI MOSFETs from DC to RF frequencies. The effect of the back-gate bias on non-linearity of the device is studied by means of 2nd and 3rd harmonic distortions (HD2 and HD3) extracted from dc I-V curves as well as from large-signal RF measurements using 1-dB and IP3 points. It is shown that the non-linearity is reduced by applying a positive back-gate bias. The reasons for this reduction are increasing of “effective body factor” and lesser mobility degradation with increase of the positive back-gate bias.

The Drain Induced Barrier Lowering (DIBL) behavior in Ultra-Thin Body and Buried oxide (UTBB) transistors is investigated in details in the temperature range up to 150°C, for the first time to the best of our knowledge. The analysis is based on experimental data, physical device simulation, compact model (SPICE) simulation and previously published models. Contrarily to MASTAR prediction, experiments reveal DIBL increase with temperature. Physical device simulations of different thin-film fully-depleted (FD) devices outline the generality of such behavior. SPICE simulations, with UTSOI DK2.4 model, only partially adhere to experimental trends. Several analytic models available in the literature are assessed for DIBL vs. temperature prediction. Although being the closest to experiments, Fasarakis' model overestimates DIBL(T) dependence for shortest devices and underestimates it for upsized gate lengths frequently used in ULV (ultra-low-voltage) applications. This model is improved in our work, by introducing a temperature-dependent inversion charge at threshold. The improved model showed very good agreement with experimental data, with high gain in precision for the gate lengths under test.

We report on the layout effects in strained SiGe channel FDSOI pMOSFETS down to 20nm gate length. Two SiGe integration schemes are compared: the SiGe-first approach, with Ge-enrichment performed prior to the STI module and the SiGe-last approach using only a SiGe epitaxy after the STI module. We evidence reduced layout effects in the SiGe-last integration featuring Si/SiGe bilayer. SiGe-last shows −39% mobility for 170nm narrow 2µm long channel, but +21% Ieff at Lg=20nm and gate-to-STI distance of 59nm. It is translated into a −15% delay reduction for ring oscillators of 1-finger inverters. Layout dependences are explained by physical strain measurements and reproduced by a stress-based electrical model.

We present deep insights on the integration and physics of two new strain boosters for FDSOI CMOS. "STRASS" and "BOX creep" techniques (for tensily and compressively stressed channels, respectively) are for the first time integrated in a localized manner on a state-of-the-art 14nm FDSOI route. STRASS enables to achieve +1.6 GPa in SOI active regions (w.r.t. +1.3 GPa for thin BOX sSOI). BOX creep process leads to more than +10% in hole mobility and +6% in Ieff(Ioff) plots. The BOX creep efficiency is investigated with respect to device dimensions: the electrical data evolution matches the proposed mobility model based on 2D simulated stress profiles.

A novel dual isolation scheme with both Shallow Trench Isolation (STI) and local oxidation, so called Dual Isolation by Trenches and Oxidation (DITO), is presented to maximize the stress induced by SiGe channel and the back-biasing efficiency at the same time in FDSOI technology. DITO integration experimentally demonstrates +36% pMOSFET drive current at same leakage, which is translated into −23% ring-oscillator delay reduction at a supply voltage of V dd =0.8V. It is found that this gain is attributed to 0.45GPa saved compressive stress in the longitudinal direction, compared to the standard STI isolation. On top of that, DITO enables the Vt tuning in an extended range for both nMOS and pMOS independently through back-bias application in both reverse and forward modes. +29% and 1 decade leakage extensions are provided by this full range Vt tuning compared to the standard single STI and well FDSOI architecture where only one back-bias mode is allowed. DITO thus leverages highly-stressed and highly-tunable devices for both high performance and low power applications.

We report on the main local layout effect in 14nm Ultra-Thin Buried oxide and Body Fully Depleted Silicon On Insulator (UTBB-FDSOI) CMOS technology [1]. This effect is demonstrated by Nano-Beam Diffraction to be directly induced by the strain in the SiGe channel and reproduced by an accurate electrical compact model. An original continuous-RX design optimizes the stress management, maintaining longitudinal stress component while relaxing the transverse one. A 28% ring oscillator delay improvement is experimentally demonstrated at same leakage for 1-finger inverter at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> =0.8V supply voltage and a frequency gain up to 15% is simulated in a critical path of an A9 core.

Strain boosters are an effective way to improve performances in advanced CMOS FDSOI devices. Hole mobility is higher in pFETs with compressive channels. Meanwhile, electron mobility is higher for nFETs with tensile channels. We present an alternative technique to blanket sSOI substrates. The efficiency of the "Strained Silicon by Top Recrystallization of Amorphized SiGe on SOI" technique has been previously successfully demonstrated on blanket SOI (+ 1.6 GPa tensile strain achieved). Here we demonstrate a simple and efficient STRASS module integration in an advanced FDSOI route (14 nm design rules) which allows to cointegrate tensile Si for nFETs and unchanged pFETs. After pFETs have been protected (SiN), the STRASS technique has been used in the SOI nFET patterns. This process requires SiGe selective epitaxy, buried amorphization by ion implantation, recrystallization and SiGe removal. Raman spectroscopy is used to characterize the stress in Si areas with respect to process conditions (implantation, active area dimensions). Moreover, the mechanisms of SiGe relaxation will be discussed as function of device dimensions and SiGe layer properties (thickness, Ge content). We demonstrate the successful integration of localized STRASS module: tensile Si patterns (for nFETs) with a level of stress of + 1.6 GPa, cointegrated with unmodified pFETs. (C) 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim

We have physically and electrically characterized pMOSFETs of compressively strained SiGe channel built on Ultra-Thin-Body and Buried-Oxide Fully-Depleted-Silicon-On-Insulator (UTBB FDSOI). Such a channel greatly contributes to the FDSOI CMOS high-performance at the 14nm node. At the same time, it induces strong layout effects, which are reported and explained in this paper. They can be reproduced by an accurate physics-based electrical model, which enables us to predict the device and design performance for various technological configurations: germanium concentration in the channel, isolation and channel process integration. In order to mitigate the impacts of the SiGe channel relaxation, we have studied two kinds of solutions. First, technological solutions are possible, leading experimentally to a -15 percent delay reduction for a ring-oscillator of 1-gate finger inverters at 0.8V supply voltage. Secondly, we demonstrate the benefits induced by smart design layouts, enabled by process integration goodies and some layout constructs. Namely, a continuous-RX design, which consists in a long active line configuration, optimizes the stress configuration, maintaining a high level of longitudinal compressive stress, while relaxing the transverse one. A 28 percent ring oscillator delay improvement is experimentally demonstrated at a given leakage for 1-finger inverter at 0.8V supply voltage. This demonstrates the interest of process/design co-optimization of strain-induced layout effects. Finally, we discuss the technological knobs and especially the strain boosters that can furthers the scaling of FDSOI below the 14nm node: SiGe channel and source/drain of high-Ge content, influence of the surface orientation and channel direction, as well as the gate last integration.