For the 32nm logic technology and beyond, more stringent specifications in terms of dimensions and materials integrity continue to drive the cleaning process improvements. In this paper, post-etch wet cleaning was optimized in order to address CD loss issues and metal hard mask cleaning improvement in a Trench First Hard Mask (TFHM) backend architecture. Based on materials compatibility tests and electrical results, this wet clean process should also be fully compatible with a Via First Trench Last (VFTL) architecture.

In this article, focus has been made on two topics: the SiGe sensitivity to wet Front-End-Of-Line (FEOL) surface preparations and the SiGe/Oxide interface. Depending on the FEOL cleaning process, the chemical oxide growth on SiGe and the associated consumption can be tuned in order to precisely control the oxide thickness and the material loss. In this case, HF last surface preparation presents good performances but his final hydrogen passivation gives a SiGe surface too sensitive to furnace oxidation steps. Using SIMS, AR-XPS and AFM analyses, we show a Ge segregation at the interface or/and a Stranski-Krastanov (SK) relaxation. Finally, a wet clean process with a final hydroxyl passivation is preferred and presents a good compromise between material loss, chemical oxide growth and roughness at the SiGe/Oxide interface.

Integrating multiple gate oxides on a same die requires a proper definition of their respective active area (fig. 1). First the thick gate oxide is grown, and covered by some photoresist. Then a wet etch removes this oxide on the die areas where the resist has been developed. Finally, after resist stripping and surface cleaning, the thin gate oxide is grown. The interaction between the thick oxide surface, the resist and the etchant makes the wet etch challenging. This paper deals with some characterizations and solutions to improve this process.

This paper is dedicated to the memory of Professor Marius Chemla. It is an illustration of the possibility to investigate nanoscale processes at silicon/electrolyte interface using a home built cell and conventional electrochemical techniques, as the study of the silicon/electrolyte interface was his main scientific activity during the last twelve years. Wet chemical treatments have until now been the main processes used in the semiconductor industry to remove metallic, organic or inorganic contaminants from the silicon wafer surfaces, These contaminants are responsible for dielectric breakdown. The most often used cleaning solutions are HF, for dissolving native oxide and oxidizing agent such as H2O2, mixed with aqueous NH4OH or HCl to remove inorganic and metallic particles. We studied the electrochemical processes of silicon surface contamination in HF solution by traces of copper ions at the ppb level, and proved that the measurement of accurate open circuit potential, was sensitive enough to study the generation of nanoscale copper nuclei, on top of the silicon surface: the silicon surface acting in this case as a very efficient sensor. Another topic where electrochemistry was extremely powerfull is the growth of ultra-thin silicon oxide films in basic or acidic oxidizing solutions, followed in situ by electrochemical impedance spectroscopy. Nyquist plots complemented by infra-red spectra lead to a comprehensive study of the silicon oxide film growth, a few angstrom thick.

For a comprehensive interpretation of the electrochemical processes occurring at a semiconductor/electrolyte interface, an accurate value of the flatband potential versus the reference electrode is needed together with the current/voltage response. The present work is mainly devoted to the analysis of impedance diagrams recorded with n- and p-type silicon electrodes in the dark, in a pure diluted HF solution under different bias values, the potential range being chosen so as the dc current is maintained at a low value, e.g. less than 5 mu A cm(-2), and even less than 10 nA cm(-2) in the case of p-type Si under cathodic polarization.Two series of impedance diagrams were recorded. Firstly, the bias value was settled in the potential range where the depletion layer was generated within the semiconductor substrate. In this condition, the high resistance of the space charge region and the resulting low value of the dc current permitted to obtain well-defined semicircles leading to the derivation of both R and C values equivalent to the depletion layer charge distribution. The method based on the analysis of the voltage dependent R-value was compared to the usual Mott-Schottky plot treatment, and proved to be efficient for the determination of a reliable value of the flatband potential versus the reference electrode.In the second series, the analysis of the impedance diagrams was focused on the range of potentials corresponding to the onset of an accumulation layer within the semiconductor. In the case of p-Si, this condition corresponds to the rapid anodic etching of the silicon substrate. At a particular value of the bias, an important induction loop was observed in addition to the usual capacitive behaviour. A Fourier transform treatment demonstrated that the impedance components were interrelated to the time dependent current response under constant bias potential. Then, simultaneous experiments based on chronoamperometry measurements suggested that the electrochemical processes involved in the reaction of Si substrate with HF solution was correlated to a two-step charge transfer mechanism. This interpretation is valid for both the inductive loop obtained in electrochemical impedance spectroscopy and the rise of current versus time observed in chronoamperometry. (C) 2005 Elsevier Ltd. All rights reserved.

This paper investigates low temperature cleaning steps solutions (T°<30°) developed to enhance the 65nm transistor performance. A complete cleaning recipes optimization is realized in term of silicon consumption and defectiveness for pre-furnace clean (RCA or HFRCA), post gate etch clean PGEC (HF-SPM-SC1) and post ash clean PAC (SPM–SC1) operations. The silicon recess and the dopants consumption are reduced by using low temperature SC1 steps. Transistor drivability is improved by 8% and 7% for NMOS and PMOS respectively.

Today, batch processes are widely used in the industry for all surface preparation applications. This batch strategy, which is also used in the thermal treatment area (furnaces), is one of the main detractors for cycle time and fab flexibility in ASIC world. This statement combined with the footprint, the price and the very high DIW consumption of the 300mm conventional wet benches (WB), has been the main driver for the introduction of single wafer cleaning tool in the Crolles 2 facility.

For the wet cleaning of silicon surfaces, a few new reactants, such as ozone dissolved in UPW, have been proposed to replace the original RCA process using H2O2 solutions. In the present work we describe, for the first time, the mechanism of silicon surface oxidation by dilute solutions of elemental chlorine. Upon reaction with this highly oxidizing agent, the open circuit potential shifted immediately to positive values, the effect being identical for both n- and p-type Si substrates. The surface transformation was firstly investigated by electrochemical impedance spectroscopy which showed successive semicircles representing RC equivalent circuits, revealing a gradual growth of an insulating layer. XPS recordings demonstrated unequivocally the formation of a pure and uniform chemical oxide layer, the possible contamination by Cl element being negligible. The analysis of the charge transfer reaction by voltammetry led to the conclusion that the exchange between the semiconductor and the solution involved positive holes. The reduction current, at a negative bias potential, was extremely small with p-type Si as a consequence of a depletion layer appearance. On the contrary, in n-type substrates, an accumulation region was formed, so that the electric field, as high as 107 V cm-1, will promote a conduction mode through the insulating oxide layer. This novel technique of surface treatment seems promising with respects to the economy and environmental requirements, and also for the possible subsequent growth of multi-layer high-k dielectric structures.

The differential capacitance Of SiO2 ultra-thin layers on Si substrate is greatly sensitive to the space charge generated within the semiconductor. In the potential scan, the determination of the capacitance/voltage characteristics in MOS devices is hindered by the high value of the tunneling leakage current. In this work, the difficulty was overcome by careful measurement of the impedance diagrams using a semiconductor/oxide/electrolyte (SOE) structure, under zero current flow. Depending on the bias potential we obtained RC equivalent circuits corresponding either to the depletion layer or to the oxide dielectric film. A novel aspect of the work is that both R and C components were derived from the data processing.In a previous work the investigation was focussed on the depletion layer, and lead to values of the resistance term in the range of a few kOmega to a few MOmega cm(2), while the capacitance value was a few 10(-2) muF cm(-2). These results were consistent with a theoretical treatment of the bias voltage dependence of the charge distribution near the flatband potential, and constitute a new technique for the determination of the fb potential versus a reference electrode.The present work is devoted to the electrical properties of the Si surface oxide layer. The leakage resistance term of the thermal oxide layer, a few nm thick, was found equal to several 10(8) Omega cm(2). But, the electric field within the semiconductor is not effective for the full charge of the oxide capacitance even when the polarization creates an accumulation layer. In accordance with the computed electric field within the semiconductor, the right value of the capacitance can be reached easily when the wafer is submitted to light radiation and provided the polarization of the substrate is such as to generate an inversion layer. This property leads to an accurate method for ultra-thin insulators characterization excluding tunnel leakage current. (C) 2003 Elsevier B.V. All rights reserved.

Neutron reflectivity was applied to the study of ultrathin silicon oxide films, of interest due to the requirement for reduced dimensions of the elemental components in microelectronic devices [I. Eisele and W. Hansch, Thin Solid Films 369, 60 (2000); C. Battaglin et al., Thin Solid Films 351, 176 (1999)]. Silicon oxides were prepared using three different ways: Chemical, electrochemical, and thermal oxidation. From neutron reflectivity, it was possible to derive the oxide thickness, the Si/SiO2 interface roughness, and the density of the layer. In complementary measurements, the chemistry of the chemical and thermal surface layers was obtained by infrared spectroscopy. The anodic oxides were found to be as dense as thermal oxides, but the chemical one was less dense. This result was checked by Fourier transform infrared spectroscopy.

The zero current impedance of a silicon substrate in a semiconductor/oxide/electrolyte structure was used to identify the contribution of the depletion layer under various bias potentials. Careful measurements using p-Si in a HCl solution within the potential range of 0 to -1 Vvs. a saturated calomel electrode (SCE) led to the determination of the corresponding equivalent circuits as a function of the bias potential. Modeling the circuit as a constant phase element proved that the imaginary component was a pure capacitor C-SC in parallel with a pure resistance R-SC. Experimental data showed that these two components undergo a steep variation when the system approaches the silicon flatband potential situation. A novel fundamental development is presented, assuming that the gradient of potential inside the material is small enough for a simplified treatment based on the linearization of the exponential function. The steep increase in the vicinity of the flatband potential of the space charge capacitance and conductance was confirmed. This constitutes a useful tool for electrochemical studies to determine the flatband potential and band curvature as a function of the sample potential measured vs. the SCE reference electrode. (C) 2002 The Electrochemical Society.

Neutron reflectivity was applied to the study of ultra-thin silicon oxide films, under investigation due to the demand for reduced dimensions of the elemental components in microelectronic devices. Silicon oxides were prepared through three different ways: chemical, electrochemical and thermal oxidation. From neutron reflectivity it was possible to obtain the oxide thickness, the Si/SiO 2 interface roughness, and the density of the layers. Impedance spectroscopy was also performed before and after the growth of an anodic oxide, in order to characterize the electrical behaviour of the interface. In complementary measurements, the chemical and thermal surface layers chemistry was obtained by infra-red spectroscopy. The anodic oxides found to be as dense as thermal oxides, with the chemical one, the less dense. This result was checked by FTIR.

In this work we investigate the efficiency of single wafer wet cleaning processes to remove metallic surface contamination on the Oasis Clean single wafer processing tool. We studied a single step modified SC1 process - with chelating and surfactant additives, called AM-Clean - as well as two cleaning step processes. As such we were able to select single wafer AM-Clean process sequences that are compatible with 0.13mum and beyond FEOL technologies and process flows to substitute conventional batch cleaning processes.

The aim of the present work is to analyse the specific contribution of the differential capacitance of SiO2 ultra-thin layers to the impedance diagrams of Si/Oxide/Electrolyte (SOE) structures. In usual techniques dealing with MOS devices, the determination of the capacitance/voltage characteristics in MOS devices is hindered by the high value of the tunneling leakage current. In this work, the difficulty was overcome by careful measurement of the impedance diagrams using a SOE structure, under zero current flow. With this novel technique we obtained one RC equivalent circuit when the bias potential corresponded to the accumulation regime, whereas two well separated RC circuits appeared under the depletion regime. An interesting feature of the method is that both R and C components were derived from the data processing. It is known that the measured value of the oxide layer capacitance is sensitive to the charging process of the space charge layer. We observed that the experimental, values of the depletion layer capacitive term were in the range of a few 10(-2) muF cm(-1). These results were consistent with a theoretical treatment of the charge distribution near the flatband potential. In the case of a thermal oxide insulating layer a few nanometers thick, the capacitance was found equal to a few muF cm(-2), in agreement with the computed value from the SiO2 oxide thickness. The local electric field is effective for the full charge of the oxide capacitance only under light radiation, and leads to an accurate method for ultra-thin insulators characterization excluding tunnel leakage current.

Advanced 300-mm application specific integrated circuit/system-on-chip (ASIC/SOC) fabs with multiproduct and multiprocess models will require both a high level of flexibility and efficiency to achieve cost effective manufacturing cycle times. One of the main detractors for cycle time and fab flexibility is a hatching requirement on certain types of processing that makes. lots waiting for the batch to be completed and generates wip bubbles downstream. This paper reviews the front-end steps within a semiconductor manufacturing flow where hatching requirements may be replaced by single-wafer or mini-batch alternatives for improved cycle time. Encouraging process results for front-end applications for potential single-wafer replacements are presented. It is demonstrated that single-wafer oxidation, LPCVD and cleaning offer a large potential cycle time, gain but currently have different levels of maturity as potential batch technology replacements.In addition to the process feasibility, a DOE based on dynamic simulation is conducted enabling the quantification of potential gains in cycle time obtained by switching to single-wafer or mini-batch strategy instead of batch strategy, preferring integrated metrology and reducing mini-lots size. It shows that, in comparison to the baseline model (100%), the manufacturing cycle time may decrease down to 65% for mini-lots and to 78% for standard production lots.

A careful study of the impedance at zero current of a silicon substrate in a semi-conductor/oxide/electrolyte (SOE) structure permitted to identify the contribution of the depletion layer under various bias potentials. Modelling the equivalent circuit proved that the imaginary component was a pure capacitor C in parallel with a pure resistance R. Experimental data showed that these two components undergo a steep variation when the system approaches the silicon flat band potential situation. A theoretical development is presented under the assumption that the gradient of potential inside the material is small enough for a simplified treatment based on the linearization of the exponential function. The steep increase in the vicinity of the flat band potential of the space charge capacitance and the conductance was confirmed. It constitutes a useful tool for electrochemical studies to determine the band level curvature as a function of the sample potential measured vs. a reference electrode.

Wet ultra-thin silicon oxides, resulting from the oxidation of hydrophobic monocrystalline silicon surfaces in oxidizing cleaning solutions, were investigated with electrochemical methods. We used SC1 (NH4OH: H2O2: H2O) and SC (HCl: H2O2: H2O) media, and the build-up 'of the silicon oxide on the surface was monitored in situ, by electrochemical impedance spectroscopy (EIS). In SC1 solution, the Nyqqist plot reached a limiting semi-circle after ca 3 hours, leading to a resistance value, tenfold less than in acidic SC2 solution, leading to the conclusion that the oxide layer was much more permeable to ions in SC1 electrolyte than in SC2 solution. Ellipsometric determination of the oxide thickness indicated that a limiting value was attained after only a few minutes in; SC1 solution. These results let us to infer that the SC1 media affected both the thickness and the structure of the ultra-thin silicon oxide, a conclusion supported by infra-red spectroscopic investigations.

With the evolution of the scaling down of the technology, the gate oxide thickness and the applied voltage of the devices are reduced. But for I/O connection, higher applied voltage is required. Consequently, two thickness of Gox or "Dual Gate Oxide", called "DGO" below, needs to be built on the same device [1]. This paper describes the process & equipment optimization of the sequence of steps using wet chemicals on 8" wafers, i.e. oxide etching, photo-resist stripping and surface preparation before Gox growth, in an industrial environment. In particular, the oxide etching before photo-resist stripping is found to be key for the control of the Gox thickness. Some ideas are also given for the evolution of this process sequence for the generation of 0.12 mum Cmos technology on 12" wafer.