In this work, P-MOS transistors of advanced bulk technology integrating high K/metal gate and SiGe channel are considered. An exhaustive study of threshold voltage (Vt), current gain factor (beta), and drain-current (Id) mismatches with different Ge proportions in the channel is performed, in linear regime, for transistors with and without pocket implants. A comparison between channels with and without Germanium and with different proportions of Germanium is considered. A global improvement of P-MOS transistors electrical parameters mismatch is observed with the introduction of Ge in the channel. Some explanations for this improvement with the introduction of Ge are proposed. (C) 2013 Elsevier Ltd. All rights reserved.

The Ge impact on the threshold voltage (VT) and the flat band voltage (VFB) of SiGe pMOSFETs is evaluated through a comparison of experiments and simulations with various SiGe thicknesses and Ge contents. Increasing Ge content shifts linearly (VT–VFB) in full agreement with Poisson–Schrodinger simulation results accounting for adequate band discontinuity and strain. An additional VFB shift is needed to match the measured CV in accumulation, revealing a work function modification or the presence of dipole in the gate stack due to Ge diffusion.

Low-frequency noise (LFN) of high-k/metal stack nMOS and pMOS transistors is experimentally studied. Results obtained on 32-nm complementary metal-oxide-semiconductor (CMOS) technologies, including LFN spectra and normalized power spectral density data analysis, are presented. These results indicate that the carrier number fluctuation is the main noise source for both nMOS and pMOS devices. As noise performance may strongly vary between different devices on one chip, the variability of the LFN when scaling down devices was also evaluated. A model known in the literature was used and enhanced in order to understand the noise level variability. A statistical analysis of the noise variability is also presented showing the dependence of the standard deviation with the device area. The comparison with former results from 45-nm poly/SiON technology demonstrates a better control of noise variability in the 32-nm CMOS technology.

In this article, focus has been made on two topics: the SiGe sensitivity to wet Front-End-Of-Line (FEOL) surface preparations and the SiGe/Oxide interface. Depending on the FEOL cleaning process, the chemical oxide growth on SiGe and the associated consumption can be tuned in order to precisely control the oxide thickness and the material loss. In this case, HF last surface preparation presents good performances but his final hydrogen passivation gives a SiGe surface too sensitive to furnace oxidation steps. Using SIMS, AR-XPS and AFM analyses, we show a Ge segregation at the interface or/and a Stranski-Krastanov (SK) relaxation. Finally, a wet clean process with a final hydroxyl passivation is preferred and presents a good compromise between material loss, chemical oxide growth and roughness at the SiGe/Oxide interface.

We demonstrate for the first time high-performant planar multi-gates devices with Si-conduction channel of 4nm, allowing drive current up to 1350μA/μm @Ioff=0.4nA/μm (Vdd=1.1V, CET=1.9nm). But as future multi-gates transistors need to have reduced capacitances and a simple robust process, we also demonstrate in this paper an ideal planar self-aligned solution, based on the direct exposure of a HSQ layer through a 5nm Si-channel. This opens the way to an easy planar multi-gate process for ultimate CMOS (11nm node & below), fully co-integrable with conventional devices.

J.-L. Huguenin1,2, S. Monfray1, G. Bidal1, S. Denorme1, P. Perreau3,1, N. Loubet1, Y. Campidelli1, M.-P. Samson1,3, C. Arvet1,3, K. Benotmane3, F. Leverd1, P. Gouraud1, B. Le-Gratiet1, C. De-Butet3,1, L. Pinzelli1, R. Beneyton1, S. Barnola3, T. Morel1, A. Halimaoui1,3, F. Boeuf1, G. Ghibaudo2, T. Skotnicki1. 1 ST Microelectronics, 860 rue Jean Monnet, 38926 Crolles, France ; 2IMEP-LAHC, 3 parvis Louis Néel, BP 257, 38016 Grenoble Cedex 1, France ; 3 CEA-LETI 17 rue des Martyrs, 38054 Grenoble, France

The objective of this paper is to present the successful co-integration of Logic Ultra-Thin Body and Box (UTBB) devices and bulk-Si I/O devices on the same chip. The UTBB transistors are integrated locally on a Bulk wafer with the Localized Silicon On Insulator (LSOI) process technology with HfO2/TiN gate stack for low power applications. I/O co-integrated Bulk devices have a thicker interfacial SiO2 under the HfO2/TiN stack to be compatible with the I/O higher voltage. Both performances of logic UTBB and I/O bulk devices are presented.

This paper proposes a new expression unifying all transport mechanisms (drift-diffusion, velocity-saturation and quasi-ballistic). This enables an experimental extraction of the limiting velocity and also, for the first time, a determination of its nature (thermal injection or velocity saturation). We show that the observed increase in the limiting velocity in short and strained devices was confusingly interpreted as an evidence of increasing ballisticity. At least down to 20nm channel length, the transport remains velocity-saturation limited. However, the good news we confirm experimentally is that V sat increases itself in short and strained devices. This promises an increase in I on , even if the nature of the transport is velocity-saturated. This new findings open doors for the study and optimization of transport in advanced CMOS technologies.

In this study, a new technique to extract the S/D series resistance (R-sd) from the total resistance versus transconductance gain plot R-tot(1/beta) is proposed. The technique only requires the measurement of I-d(V-gs)vertical bar(Vgt) and beta, allowing fast and statistical analysis in an industrial context. Unlike the usual R-tot(L)-based techniques, it has the advantage of being insensitive to the channel length and mobility variations and finally enables to extract very accurate values for R-sd(V-gs) and the effective mobility reduction factor mu(eff)(V-gt)/mu(eff)(0).

En depit des defis technologiques a surmonter lors de la reduction d'echelle, la technologie sur silicium assif (bulk) reste attractive grâce son cout modere. L'augmentation du dopage est un des leviers utilises pour ontrecarrer les effets de canaux courts. Si cette solution reste contraignante en termes de performances (car elle entraine une diminution de la mobilite et une augmentation de la variabilite), l'augmentation du taux de balisticite sur les petites longueurs de grille laisse entrevoir la perspective d'un fort courant Ion, peu dependant de la mobilite. Cette vision semble attractive, mais la litterature porte peu d'attention a discriminer le phenomene de vitesse de saturation (vsat) du phenomene d'injection a la source (vinj). Pourtant, chacun d'eux peut etre LE mecanisme limitant Ion selon le flux de porteurs est limite par la capacite d'injection ou bien par les proprietes de transport du canal. Ce papier ce focalise sur la determination de la vitesse limitant le transport en considerant les deux approches comme probables.

For the first time we demonstrate the CMOS integration of undoped fully-depleted Ultra Thin Body and BOX devices (UTB2) with (110)/(100) substrate crystal orientation for pFET and nFET respectively. For this, we used an original 3D-folded Bulk+/Silicon-On-Nothing (SON) process on DSB substrate. Resulting multi-surface orientations devices are studied.

This paper reports a new methodology to monitor L-dependent mobility degradation based on empirical modeling of experimental results. This method allows benchmarking the impact on mobility degradation of different technological modules, thus giving some guidelines for device optimization. Introduction As channel length L of MOSFETs is scaling down, carriers’ mobility μ is degraded by additional scattering mechanisms with a dramatic impact below 100nm. As reported by Andrieu et al. [1] and by Cros et al. [2] (Fig.1), this mobility crisis affects both electrons and holes. Moreover, this degradation has been measured for both poly-Si gate and metal gate [3], for both high-K and SiO2 [4], for strained and unstrained devices [1,3], for doped and undoped channel [2,4] and also whatever the device architecture: Bulk [1], SOI, [4,5], Gate-All-Around [2] or FinFET [6]. This μ(L) degradation was confirmed whatever the extraction method, i.e. Y-function, Split-CV or magneto-resistance [7], and cannot be solely explained by ballistic effects [8,9]. Unfortunately, mobility falls is a sign of a poor quality of the transport in the channel keeping us away from the ballistic regime. Whatever the conduction regime (ballistic or drift-diffusion), the on-state current will be limited by a maximum velocity that can be expressed as vlim = min(vsat,vinj) [10]. As shown in Fig.2, strong mobility degradation on short devices prevents from reaching the velocity limit, i.e. maximum on-current. Some authors [7,11] have identified those additional scattering mechanisms as impurity Coulomb scattering while neutral defects have been suggested by others [2,4]. This statement gives ground for a systematic examination of μ(L) degradation in order to establish guidelines for device optimization even if the precise origin of those additional scattering mechanisms is still not fully understood. Extraction Methodology & μ-Degradation Modeling A handy tool for extracting the mobility and monitoring its length dependence is the low field mobility μ0=μeff(Qinv≈0)=β0CoxLeffWeff. β0 at low VDS (<<VDsat) is extracted from the Y-function [12] Y(VGS)=ID/gm while effective channel length and width (resp. Leff and Weff) and gate oxide capacitance Cox are obtained independently from gate-to-channel CGC(VGS) measurements [13]. The notion of μ0 is illustrated by Fig.3. It is also worth noticing that classical Coulomb scattering and surface roughness terms do not significantly alter μ0 at 300K. Using first order θ1 and second order θ2 mobility attenuation parameters, μeff in strong inversion can be reconstructed, showing good agreement in Fig.4 with RSD-corrected split C-V extraction [14]. The use of μ0 as a mobility indicator has been validated in Fig.5 by comparing it to split C-V extraction for different Leff, clearly showing that μ0 and μeff are degraded in similar way as Leff is reduced. All our μ0 extraction have been performed vs. Leff to fairly compare the different technological splits. In order to construct our guidelines, we have introduced a new length dependent mobility degradation fitting model: 1/μ0(Leff)=1/μmax+αμ/Leff. The two fitting parameters are the maximum mobility μmax [cm.V.s], which is generally equal to the “long” channel mobility, and a mobility degradation factor αμ [nm.V.s.cm]. Fig.6 illustrates the different kinds of μ0(Leff) curves that can be obtained, αμ=0 meaning zero degradation and thus a constant μ0. However, it should be noted that αμ cannot be lower than its minimum value given by the ballistic mobility [15] αμbal= (2kT/q)/vinj, vinj being the injection velocity at source (αμbal =0.04 or 0.08 nm.V.s.cm for electron and hole respectively). Experimental Results Gate stack: Gate stack impact on μ0 was examined in Fig.7 & Fig.8. In Fig.7, two plasma nitrided SiON gate oxide thicknesses (12Å vs. 17Å) were compared for the same poly-Si gate, showing more degraded electron mobility for the thinner 12Å oxide. In Fig.8, we have found that nitrided metal gates (TiN, TaN) lead to more degraded electron mobility than the non-nitrided TaC metal gate. Those results are suggesting that N-species in the gate oxide and/or in the gate electrode lead to a lower long channel mobility in agreement with [16], but also to a higher αμ i.e. to stronger scattering mechanisms. Channel doping: Effect of channel doping was examined in Fig.9 using ultra thin body (UTB) structures in both cases (doped vs. undoped) for avoiding short channel effects disturbances. Devices fabricated using Silicon-On-Nothing (SON) technology have bulk S/D [17]. We found that increasing the channel doping is lowering the long channel electron mobility but has no significant effect on additional scattering mechanisms since close αμ values were found. Junction architecture: Since neutral defects introduction is likely related to the junction (S/D+LDD) ion implantation (I/I), S/D architecture appears as a key module for improving mobility degradation. Cros et al. have already shown in [2] that an increase of the temperature during the RTP activation anneal could cure partially the mobility degradation. Taking the problem differently, we have examined if it was possible to improve mobility degradation by changing I/I conditions (species, energy, dose). Results in Fig. 10 are demonstrating that S/D architecture optimization is possible even when reducing the RTP temperature. Mobility boosters: After having examined some possible causes of degradation, we have now investigating the effects of mobility boosters on mobility degradation. Local process induced stress (PIS) engineering by using eSiGe stressors is studied in Fig.11, while surface orientation is considered in Fig.12. Even if both strategies have an impact on holes’ μmax, only local PIS which is also L-dependent [18] significantly improves αμ. Discussion & Guidelines Seeing the strong degradation of the mobility, one could think that any mobility improvement is not relevant since all strategies will finally have the same mobility at very short gate length. Using our model, we have extrapolated from the measurements the resulting mobility at Leff=10nm in Fig.13. We can see that mobility improvement is still possible even at 10nm if well optimized. We have also investigated a possible link between μmax and αμ in Fig.14: no clear correlation was found between the two parameters meaning that they are needed to monitor the mobility degradation. Thus we have introduced a new figure of merit η=μmax/ αμ. Higher η is, higher the short channel mobility will be and closer to its limiting velocity the device will operate. Finally, we give some guidelines, based on this work in Fig.15 in order to limit μ(L) degradation. Conclusion Using a new monitoring method based on empirical modeling of μ(L) degradation, we have systematically examined the impact on μ(L) of the gate stack, channel doping, junction architecture and mobility boosters. It has been found that this degradation is not ineluctable and that working on key technological modules would help us to get closer to the ballistic regime. Acknowledgments The authors thank Process Integration teams and ST-LETI Advanced R&D for devices fabrication. This work was partially supported by IST-PULLNANO project. 0 50 100 150 200 250 300 350 400 450 0.01 0.1 1 Effective Channel Length Leff (μm) Lo w F ie ld M ob ili ty μ 0 ( cm 2 .V -1 .s -1 )

This work presents an experimental study in order to evaluate the quality of transport in state-of-the-art gate-all-around devices. 25 nm times 20 nm times 10 nm (LxWxT Si ) silicon channel devices with metal/high-k gate all-round stack were characterized electrically in terms of mobility and limiting velocity in order to evaluate the possible occurrence of ballisticity. Conclusions are finally presented in the scope of elementary circuit perspectives.