There is an ongoing need in the microelectronics industry to increase circuit density in multilevel back-end-of line (BEOL) interconnects to improve the operating speed and reduce power consumption. One way to maintain capacitance-resistance (RC) performance, without de grading yield or reliability is through introduction of porous ultra low-kappa materials (ULK) as interlevel dielectrics (ILD). This paper presents the ability to tune ULK films through simple processing optimization steps to meet the specific integration requirements. Balancing composition of the film to minimize damage needs to be coupled with improving mechanical integrity for packing compatibility.

A cost effective 28nm CMOS Interconnect technology is presented for 28nm node high performance and low power applications. Full entitlement of ultra low-k (ULK) inter-level dielectric is enabled. Copper wiring levels can be combined up to a total of 11 levels. The inter-level dielectric was optimized for low k-value and high strength. The feature profiles were optimized to enable defect-free metallization using conventional tools and processes. High yields and robust reliability were demonstrated.

Optimization of SiCOH interfacial strength to underlying SiCHN is a key requirement for establishing a reliable manufacturing process for a low k interlevel dielectric. After discovering that the interfacial failure was a near-interface cohesive failure in the SiCOH film, improved interfacial strength was accomplished by engineering a graded transition region from an initial oxide layer to the bulk SiCOH film. Film deposition conditions were tuned to provide ideal film composition profile, without any carbon spike, throughout this transition region. Deposition conditions were also optimized to avoid known problems with SiCOH, such as plasma instabilities and generation of gas phase nucleated defects. This process optimization approach has been successfully performed for 3 generation nodes (90, 65 & 45nm) involving various SiCOH versions with k=3.0, 2.7 & 2.4.

L'invention concerne une structure et un procede pour former une structure qui comprend une couche SiCOH qui presente une resistance mecanique accrue. La structure comprend un substrat qui comporte une couche de materiau dielectrique ou conducteur, une couche d'oxyde sur la couche de materiau dielectrique ou conducteur, la couche d'oxyde ne comportant sensiblement pas de carbone, une couche de transition calibree, la couche de transition calibree ne comportant sensiblement pas de carbone a l'interface avec la couche d'oxyde et augmentant graduellement sa teneur en carbone vers une couche SiCOH poreuse, et une couche SiCOH poreuse (pSiCOH) sur la couche de transition calibree, la couche pSiCOH poreuse ayant une composition homogene dans l'ensemble de la couche. Le procede comprend un procede selon lequel aucun pic de la concentration de carbone et aucune baisse de la concentration d'oxygene ne sont observes dans la couche de transition calibree.

The integration of low- and ultralow-k SiCOH dielectrics in the interconnect structures of very large scale integrated chips involves complex stacks with multiple interfaces. Successful fabrication of reliable chips requires strong adhesion between the different layers of the stacks. A critical interface in the dielectric stack is the interface between the SiCNH diffusion cap and the SiCOH inter- and intralevel dielectrics (ILDs). It was observed that, due to the original deposition conditions, the interface layer was weakened both by a low adhesion strength between SiCNH and SiCOH and by the formation of an initial layer of SiCOH with reduced cohesive strength. The manufacturing process has been modified to engineer this interface and obtain interfacial strengths close to the cohesive strengths of the bulk ILDs. This paper discusses the causes for the original low interfacial strength and presents an approach for enhancing it by engineering the interface to the cap for both the dense SiCOH and porous SiCOH ILDs.

A porous pSiCOH interconnect dielectric with a dielectric constant k=2.4 has been developed from mixtures of a SiCOH skeleton precursor and bicycloheptadiene (BCHD) and optimized for successful integration in the interconnect structure of 45 nm ULSI chip. The ulk pSiCOH is characterized by small pores, low pore connectivity, and excellent electrical properties. This paper describes the selection of the precursors, the optimization process and the properties of the optimized pSiCOH. The film has been qualified for integration in three 2X dual damascene metallization levels of 45 nm interconnects.