In this paper we demonstrate the successful integration of in-situ doped embedded Si:C stressors epitaxially grown in the source and drain areas of nMOS devices using a novel Cyclic Deposition Etch (CDE) process. These layers have substitutional C content ranging between 1% and 2% with potential of achieving even higher substitutional carbon concentration. Another distinctive feature of this process is that it allows for high in-situ P doping for ease of integration within a CMOS platform. We demonstrate superior performance of strained nMOS devices with embedded Si:C showing up to 12.5% on-state current improvement over the unstrained reference process. We report on material characterization results of embedded Si:C stressors, in particular, strain retention properties as a function of subsequent post-epitaxy processing.

Strain is introduced in the fabrication of complementary metal-oxide-semiconductor devices to enhance their channel region carrier mobility [1]. Epitaxial Si1−xGex (15–30at% Ge) or Si1−xCx (1–2at% C) are typical stressor materials. As Ge has a 4% larger lattice constant (0.566 nm) than Si (0.543 nm), Si1−xGex deposited in the source/drain (S/D) regions will induce compressive strain in the Si channel, while Si1−xCx in the S/D will induce tensile strain in the channel [2].

We report a CMOS-compatible embedded silicon-carbon (eSiC) source/drain stressor technology with NMOS performance enhancement. The integration includes up to 2.6% substitutional carbon (C-sub) epitaxial Si:C and laser spike annealing (LSA) for increased C-sub incorporation. 26% channel resistance (Rch) reduction and 11% Idlin-Ioff enhancement for 0.5% C-sub and 60% Rch reduction for 2.2% C-sub are demonstrated.