In optical fiber communication systems, intensity modulation and direct detection (IM-DD) is widely used. In contrast, coherent detection based on optical phase modulation improves receiver sensitivity compared to IM-DD. This paper describes a method for canceling optical phase noise through differential detection. This method is particularly suitable for optical fiber networks requiring high reliability, such as in-vehicle optical fiber networks. First, the principle of noise cancellation is explained, and its effectiveness is verified through theoretical analysis considering the frequency bandwidth of the analog circuits. Furthermore, the post-layout simulation results of the designed analog circuits in a 65-nm CMOS process demonstrate effective noise-canceling performance at 25 Gb/s.

This paper presents a bulk-driven low-power transimpedance amplifier (TIA) for 5 Gb/s intra-computer optical communications, implemented in 65-nm CMOS technology. The design utilizes a bulk-driven technique with shorted gate and bulk terminals to enhance the gain, along with a two-stage inverter-based amplifier with series feedback and tail-cur rent capacitance for bandwidth extension. Measurement results demonstrate a 3.76 GHz bandwidth with 0.81 mW power consumption, achieving an 82% power reduction compared to conventional low-power TIAs.

Recently, differential phase-shift keying (DPSK) modulation, which provides higher sensitivity and better noise tolerance compared to conventional modulation schemes, has attracted increasing attention in optical communication technologies. Since DPSK modulation represents data by the phase difference between adjacent bits, an NRZ-DPSK conversion circuit is required. To achieve high-speed operation, an NRZDPSK conversion circuit with a half-rate architecture employing a cross-feedback configuration is proposed. A layout design was implemented for IC chip prototyping, and postlayout simulations were conducted to compare its performance with the conventional circuit configuration. The results demonstrate that the proposed circuit configuration achieves an 80% improvement in operating speed and a 65.7% enhancement in eye-opening ratio compared to the conventional one.

Switching power conversion circuits are of great importance within a wide variety of applications, including automotive, wearable device, and so on. Their widespread use is largely due to their high efficiency and small size. However, when such circuits are subject to capacitor degradation, undesired turbulence and a degradation in the overall performance of the converter circuit can be observed. This paper investigates the effect of capacitor degradation on the occurrence of chattering in high-side gate driver circuits within power conversion systems. We introduce a simple mathematical model of a high-side gate driver circuit, which incorporates a hysteresis characteristic as a result of the under-voltage lockout (UVLO) function. We analytically derived the conditions in which chattering events occur and how the number of switching events changes. These analytical expressions were achieved by analyzing the period of the return map and identifying the thresholds that can be used to characterize the different behaviors that the system exhibits. In this work, we obtain a relationship between capacitor degradation and the chattering events.

This paper aims to enhance underwater visible light communication using a propeller LED transmitter (P-Tx) and receiver camera. Our goal is to improve the operational efficiency of remotely operated vehicles (ROVs) that survey ocean resources. P-Tx is a rotating device with blinking LEDs. By rotating P-Tx, we can generate a pseudo surface with successive light trails (light-trail surface). This technology allows the ROV to track the transmitting ROV and receive data simultaneously without mechanically adjusting the optical axis. However, with increasing distance between P-Tx and the receiver, the light gradually decreases in intensity from the edge of the light-trail surface, causing the receiver to fail to track accurately. This study proposes a robust transmitter detection method that utilizes the characteristics of the light-trail surface and improves the detecting accuracy of P-Tx on the receiving side. We show that the proposed method achieves higher transmitter detection accuracy than the conventional one.

For the realization of fully-autonomous driving systems, intra-vehicle optical networks have been proposed and developed eagerly. In this paper, the latest trends of intra-vehicle optical networks are introduced. In SiPhON, which is one of the intra-vehicle optical networks, to improve the stability of a receiver circuit for the phase-modulation-signal transmission, a delay circuit for the differential detection was designed using the 65-nm CMOS process. From the post-layout-simulation results, the appropriate delay operation at 25 Gb/s was obtained over the range from 40 degrees C to 105 degrees C.

This paper focuses on underwater visible light communication using a camera as a receiver to improve the operational efficiency of remotely operated vehicles that investigate ocean resources. This technology can realize wireless communication underwater, where wireless communication using radio waves is difficult. However, the optical axes between the transmitter and receiver must be correctly aligned before sending data in the underwater environment. We have developed a propeller LED transmitter (P-Tx) to solve this problem. The P-Tx is a rotating device with blinking LEDs. We can generate a pseudo-surface with successive light trails by rotating the P-Tx. This study calls this pseudo surface a "light-trail surface." The receiver can achieve robust transmitter detection by finding the light-trail surface using image processing without mechanical optical-axis alignment. This study also proposes a modulation method using light-trail surfaces. This study develops a prototype P-Tx and implements the proposed schemes. We then perform ISC experiments using the P-Tx and a camera to verify their communication performance.

With increasing data traffic in data centers, data capacity shortages and the increasing power consumption of network-switching systems have become serious issues. Co-packaged optics (CPO) modules using a multicore fiber and vertical-cavity surface-emitting laser (VCSEL) array are promising for addressing the above issues. Inductive peaking is an effective method for extending the frequency bandwidth of a VCSEL driver. However, it is difficult to integrate multiple VCSEL drivers on the limited chip area of the CPO module because the on-chip inductor occupies a large area. In this paper, we present a small-area and low-energy per-bit (EPB) VCSEL driver for a $65-\mathrm{nm}$ CMOS chip. We fabricated an inductive-peaking VCSEL driver using self-customized on-chip inductors. Eye opening was verified at $36 \mathrm{~Gb} / \mathrm{s}$ with a power consumption of 41.6 mW by on-wafer probing electrical measurements. We achieved an EPB of $1.16 \mathrm{pJ} / \mathrm{b}$, although the occupied core area is only $124 \times 309 \mu \mathrm{m}^{2}$.

A compact VCSEL driver circuit supporting PAM4 signals for high-speed communications is proposed. The proposed circuit achieves a wide bandwidth with active inductors that can supply a large amplitude voltage and an active feedback that applies strong negative feedback. The active inductor with level shift enhances high linearity in the output signal by overcoming limitations of the circuit bias conditions. This configuration without spiral inductors reduces the circuit area by 49% compared to the circuit designed with inductive shunt peaking. The proposed circuit was fabricated in 0.18-mu m CMOS technology. It operates at a bit rate of 6 Gb/s, consumes 124.2 mW, and occupies an integrated area of 0.115 mm(2).

An accurate evaluation of power efficiency is necessary for designing transmitters and their networks for short-reach optical links, which consume a relatively large amount of power within transmitting circuits. We propose a power efficiency estimation model of an exponential horn multi-stage inverter circuit based on large-signal analysis. Transient response formulas are derived from the static characteristics of transistors, and a formula relating the eye-opening rate, power consumption, and the transistor’s growth coefficient is also derived. The obtained formulas match well with the simulation results using a device model.

Recently, self-driving cars have been eagerly studied and developed. In such applications, to transmit large-capacity data acquired by sensor devices such as radars, LiDARs, and high-definition cameras, optical fiber networks are promising as intra-vehicle systems. One type of intra-vehicle optical network has a unidirectional optical ring topology, in which the optical receiver operates in the burst mode. In this paper, we demonstrate an adaptive time-constant-control circuit that enables a quick response to the burst signal and high tolerance to large consecutive identical digit (CID) signals received during single-ended to differential conversion according to the input data patterns. We present operating principles underlying our proposed time-constant control method. The proposed circuit is designed in a 65-nm CMOS process. The experimental results show that the designed circuit operates quickly with 5-ns settling time and has a high tolerance to a large CID length of 66 bits at 10 Gb/s.

This paper presents a gain enhancement technique for a CommonGate Feedforward Transimpedance Amplifier (CGFW TIA). The proposed CGFW TIA achieves gain improvement through a current injection technique and an additional feedback path. It is designed using a 0.18-mu m CMOS technology. Post-layout simulation results show that the proposed CGFW TIA improves the transimpedance gain by 1.76 times without an increase in power consumption compared to conventional designs.

Co-packaged optics (CPO) modules have been studied and developed for improving data capacity and reducing power consumption of data-center optical communications. In this brief, we present a 16-channel optical receiver circuit for a multicore fiber (MCF)-based CPO module in a single 65-nm CMOS chip. This chip consists of 16-channel receiver circuits, received signal strength indicators (RSSIs) and power-supply noise filters for photo detectors. Characteristics of the fabricated receiver chip using the 65-nm CMOS process were evaluated by on-wafer probing, and clear eye openings of the electrical output at 25 Gb/s were obtained in all 16-channel receivers. Additionally, an energy efficiency of 1.3 pJ/b/ch was obtained. The measurement results show that our optical receiver is suitable for MCF-based CPO modules considering both the bit rate and the arrangement of the circuit blocks.

This paper presents a regulated cascode (RGC) based trans-impedance amplifier (TIA) using an active feedback topology. The circuit topology of the proposed TIA improves the gain by applying a gain boosting amplifier to a local feedback section in our previously proposed TIA. The TIA was implemented using a 65-nm CMOS technology and consumes 24.5 mW with a supply voltage of 1.0 V. The proposed TIA had also 25 Gb/s data rate operation.

We present an area-efficient and low-power four-channel 25Gb/s trans-impedance amplifier for an Rx analog front-end (Rx-AFE) on an optical receiver. The proposed circuit features a local negative-feedback trans-impedance amplifier (TIA) to expand the bandwidth. The TIA and post-amplifier use regulated cascode (RGC) topology and two differential amplifier stages with an inductive peaking bandwidth extension technique to acquire 19.6 GHz of the -3 dB bandwidth and 53.3 dB Omega of the gain. We designed the system using a 65-nm CMOS process, and the proposed four-channel Rx-AFE TIAs achieved a small area of 300 mu m x 800 mu m per lane. From the measurement results, the differential output voltage was 160 mV at 25-Gb/s PRBS31. The test chip has also 85.0 mW of power consumption; hence, it achieves 0.85 mW/Gb/s of power efficiency.

This paper proposed a packet drop probability function with an adjustable nonlinearity parameter in random early detection (RED) for active queue management of a router to control network congestion. We investigated the effect of nonlinearity on the average queue size, average throughput, average retransmission rate, average round-trip time, and fairness index for two widely used loss-based congestion control algorithms: Reno and CUBIC. Simulations were performed with Tail-Drop and the original RED to clarify the effect of nonlinearity under different traffic loads. The results showed that the RED with a nonlinear function did not aggravate the network performance statistics because achieved high throughput while maintaining a low-queuing delay, such as the original RED with a linear function under the extremely heavy traffic condition. Under the light and the heavy traffic conditions, increasing the bending degree of the nonlinear function accomplished high throughput by preventing excessive discarding of packets.

A low-power, high-gain, and low-noise design theory for an inductor-less CMOS TIA based on MSTA is proposed. The proposed technique of current bypass and cascode connection makes it possible to reduce power consumption and improve the gain of the TIA. Using a noise canceling circuit reduces the first stage noise of the TIA. Compared to conventional circuits, the proposed circuit reduces power consumption by 46%, increases gain by 4 dB, reduces noise voltage density by up to 30%, and requires about 1/30 the circuit area. The proposed circuit was fabricated in 0.18 μm CMOS technology. The bit rate is 2.5 Gb/s, the power consumption is 18.45 mW, and the gain is 66.8 dBΩ from experimental results.

A 4-channel 25-Gb/s VCSEL driver circuit in a 65nm CMOS with a small chip area and low power consumption is presented. The proposed circuit employs an inductor-less bandwidth enhancement based on feedback topology and an unbalanced current mode logic driver core to reduce power consumption. We designed and fabricated the proposed 4-channel driver circuit in a 65-nm CMOS technology. The proposed circuit achieves about half of the power consumption and chip area of the conventional one.

In this paper, we present a multichannel vertical-cavity surface-emitting laser (VCSEL) driver for co-packaged optics (CPO) with an adaptive feedforward equalization (FFE) to improve the frequency bandwidth using a simple configuration. The proposed VCSEL driver is designed in a 65-nm CMOS process. The post-layout simulation results show that the modulating operation of the 1060-nm band VCSEL is obtained at 32 Gb/s. The fabricated VCSEL driver is tested by on-wafer probing, and the clear eye opening of the electrical output is observed. All 4 channels operate at 32 Gb/s, and the strength of the FFE can be digitally controlled. Additionally, an energy efficiency (EPB) of 1.56 pJ/b/ch is obtained. The measurement results reveal that our VCSEL driver is suitable for CPO modules from the metrics of the bit rate, EPB, and the occupied chip area.

The recent progress of in-vehicle communication networks has been highlighted by the intensive investigation of optical packet communication systems using a modulation and detection device. This paper proposes a burst-mode driver circuit with an on-chip bias switch to achieve a stable and quick response in bias switching operation. The proposed circuit comprises a driver core and two types of bias circuits. Moreover, the proposed circuit changes output bias voltages using a MOS transistor as a switch. To verify the operating principle, we design the proposed circuit using a high-voltage tolerant 65-nm CMOS technology and obtain the post-layout simulations and measurement results. As a result, we achieve quick bias switching operation with 90%faster response time than the conventional one.