The etch characteristics of Ir thin films were investigated in an inductively coupled plasma chamber, using a variety of chlorine gas chemistries, which included Cl-2/Ar, Cl-2/O-2/Ar, and BCl3/Ar, as well as fluorine-based plasmas consisting of mixtures such as SF6/Ar, SF6/He, NF3/Ar, and CF4/O-2. Under our experimental conditions, we found that the etch rates of Ir were considerably faster in fluorine-containing plasmas (similar to 30 nm/min) compared to chlorine-based mixtures (<15 nm/min). The patterning of 100 nm line/space features has been demonstrated using an organic mask. Although they show the fastest etching rates, SF6-based plasmas result in significant redeposition. In contrast, etching in CF4/O-2 leads to etch profiles that are free of redeposition or residues. The poor selectivity of the mask over Ir under the different tested conditions results in shallow sidewall angles, hence highlighting the need for an alternative mask.

This paper examines various approaches for integrating backside power distribution network (BSPDN) with nanosheet transistor technologies. Deep Trench Via (DTV) based BSPDN schemes, except for Shifted Frontside Via Backside Power rail (SFVBP), do not offer cell level scaling benefits, but via resistance of SFVBP could remain a bottleneck. Direct Backside Contact (DBC) based schemes offer best cell level scaling. A novel self-aligned backside contact (SABC) scheme integrated with nanosheet transistors is demonstrated with immunity to misalignments in backside contact formation. The structure exhibits good device characteristics and satisfactory reliability.

We present a monolithic stacked FET architecture featuring a stepped channel structure where the bottom FET channels are wider than the top. Such a design relieves high aspect ratio process challenges by reducing the total stack height and provides better performance as compared to its uniform channel width counterpart at the same footprint. In addition to the stepped channels, our integrated hardware work features top-bottom channel middle dielectric isolation, top-bottom source/drain isolation and dual work function metals. As the advanced technologies are facing significant power, performance and area scaling pressures, this work extends the narrowing road beyond the nanosheet architecture.

Several next generation integration schemes – e.g. for 3D stacked transistors, backside power distribution, and advanced packaging involve permanent wafer bonding steps and drive to sub-10nm overlay requirements post bonding. Distortion during wafer bonding is a major determinant of best achievable overlay between post to pre bonding lithography layers. Here, we investigate correlations between wafer bonding process and post bonding overlay performance through a combination of experiment and modelling. We use a custom test vehicle to collect wafer distortion data from pre- and post-bond processes, as well as overlay data after the post-bond processing steps (anneal and thin). The results establish direct relationships between incoming wafer distortion, bonder-induced distortion and post-bond lithography overlay to a pre-bond level. We also use the experimental results to validate a wafer bonding simulation model to further physical explanation of process-induced distortion. The experiment results will enable advanced wafer bonding process controls to optimize distortion and scanner overlay to meet technology targets. The results will also help guide hardware design to improve distortion fingerprints to best improve scanner overlay, as well as address the distortion challenges from incoming wafers.

For more than two decades and through approximately ten technology nodes, the semiconductor industry has relied upon Dual Damascene copper interconnects. While there is vigorous debate as to the timing and dimensions of the transition, there is a general consensus that there will eventually be a need to replace copper with a different conductor metal. Motivations include copper’s requirement for space-consuming diffusion barriers and the contributions of interfacial electron scattering to higher resistance at smaller dimensions. Researchers such as D. Galla have proposed a range of candidate conductor metals, many of which would be patterned subtractively (by depositing blanket sheets of material and then etching away the portions not required for circuity). There is a growing body of literature considering the choice of metal, methods for controlling its morphology and electrical behavior, and processes for etching it. In this study, we examine a different facet of the transition from Damascene to subtractive conductor formation, specifically the role played by sidewall spacers in pattern formation and transfer. Because the dimensions at which non-Cu conductors may become competitive are well beyond the resolution limits of single exposure EUV, it is likely that an SADP process will be used. The common approach to pattern assembly for Damascene applications is to place mandrels where Cu conductors are ultimately desired, use ALD spacers on the mandrel sidewalls to define minimum-width dielectric spaces, then add a block pattern to define larger regions of dielectric and the remaining “non-mandrel” or “anti-mandrel” conductors. Then the mandrels are removed and the openings in the spacer+block mask are transferred into the dielectric, forming the trenches which will ultimately be filled with Cu. For subtractive metal patterning, preserving the existing circuit design and mask generating infrastructure favors a different approach: mandrels would still be placed at conductor locations and ALD spacers would still be used to define minimum dielectric spaces, but anti-mandrel conductor locations would be covered by new regions of masking material (rather than openings in the block mask). Then the spacers would be removed and the mandrels and anti-mandrel masks would be used to transfer the pattern into the metal below. This study focuses on comparison of the patterning performance of the two approaches using model structures to minimize the confounding impact of the subsequent etch steps (i.e., etching into ULK or metal). Topics of particular interest include LER, LWR, CDU, pitchwalking, and the effects of local variations in pattern density. Methods to improve patterning performance for both schemes will be discussed.

IBM Research recently announced that 2nm node Nanosheet Technology is able to deliver superior density, power and performance compared to today’s 7nm FinFET technology in mass production. To enable 2nm node Nanosheet Technology, advanced patterning solutions are required. Dimensional compression drives the need for advanced patterning solutions including wider use of extreme ultraviolet (EUV) lithography. This also creates higher in feature aspect ratios, which in turn creates additional challenges during plasma etch. As aspect ratios continue to increase, difficulty with in-feature ion, radical, and volatile species transport during plasma etch presents an exceptional challenge. Dimensional scaling and wider use of EUV increases the need for further reduction of critical dimension (CD) variability, including line edge and line width roughness. The introduction of 3-dimensional gate all around nanosheet architecture has introduced an additional unique set of patterning challenges to address for coming technology nodes. When combined with dimensional scaling there is a clear need for novel advanced patterning process solutions to enable future nodes. In this presentation a variety of these challenges and the impact they will have on device and node scaling will be introduced and reviewed.

Emerging memory devices, such as MRAM, RRAM, and PCM, plays an important role in in-memory computation technology which can lead to significant acceleration for machine learning and AI applications.[1-3] The basic structure of these memory cell is simply a pillar made of a wide range of materials, however, the local CD uniformity (LCDU) of the pillars is especially crucial for these memory devices. The stringent LCDU requirement derives from either the intrinsic small resistance difference between the two memory states or the requirement for creating a large number of memory states within a small range of resistance. Apparently, the stochastic variation in physical dimension will correspond to the variation in resistance from cell to cell, which will affect the correct readout of the memory states and fail the device. Because the “local” CDU in this context refers to the variation within the memory array, i.e. typically within several um, it is almost impossible to correct by utilizing existing advanced tools or process control techniques. In this work, we will demonstrate four promising options to address the stochastic effect in LCDU of pillars: a) adopting new resists, b) PTD and NTD shrink, c) DSA, d) cross-SADP. Fig. 1 shows the general approach to achieve better LCDU by printing larger CD at litho and shrink by post-litho processing.[4] Here we carefully characterize two shrinking techniques and its efficacy on LCDU improvement. Fig. 2 shows two alternative approaches, i.e. DSA and cross-SADP.[5] We will carefully explore these four approaches for LCDU improvement with thorough characterization and analysis. Subsequent pattern transfer and the retention of the LCDU improvement and cost/quality trade-off will also be discussed. Defectivity learning will also be discussed.

The progress of using DSA for metal cut to achieve sub-20nm tip-to-tip (t2t) critical dimension (CD) is reported. Small and uniform t2t CD is very challenging due to lithographic limitation but holds the key to backend-of-the-line (BEOL) scaling. An integration scheme is demonstrated that allows the combination of design flexibility and fine, rectified local CD uniformity (LCDU). Functional electrical testable Via-Chain structure is fabricated to verify the integrity of the proposed method. Through the analysis of the observed failure modes, the process is further improved. By validating DSA for such an important patterning element as metal cut, the DSA maturity can be further advanced and hopefully move DSA closer to HVM adoption.

The key challenge for enablement of a second node of single-expose EUV patterning is understanding and mitigating the patterning-related defects that narrow the process window. Typical in-line inspection techniques, such as broadband plasma and e-beam systems, find it difficult to detect the main yield-detracting defects postdevelop, and thus understanding the effects of process improvement strategies has become more challenging. New techniques and methodologies for detection of EUV lithography defects, along with judicious process partitioning, are required to develop process solutions that improve yield. This paper will first discuss alternative techniques and methodologies for detection of lithography-related defects, such as scumming and microbridging. These strategies will then be used to gain a better understanding of the effects of material property changes, process partitioning, and hardware improvements, ultimately correlating them directly with electrical yield detractors.

We report a sub-30nm pitch self-aligned double patterning (SADP) integration scheme with EUV lithography coupled with self-aligned block technology (SAB) targeting the back end of line (BEOL) metal line patterning applications for logic nodes beyond 5nm. The integration demonstration is a validation of the scalability of a previously reported flow, which used 193nm immersion SADP targeting a 40nm pitch with the same material sets (Si3N4 mandrel, SiO2 spacer, Spin on carbon, spin on glass). The multi-color integration approach is successfully demonstrated and provides a valuable method to address overlay concerns and more generally edge placement error (EPE) as a whole for advanced process nodes. Unbiased LER/LWR analysis comparison between EUV SADP and 193nm immersion SADP shows that both integrations follow the same trend throughout the process steps. While EUV SADP shows increased LER after mandrel pull, metal hardmask open and dielectric etch compared to 193nm immersion SADP, the final process performance is matched in terms of LWR (1.08nm 3 sigma unbiased) and is only 6% higher than 193nm immersion SADP for average unbiased LER. Using EUV SADP enables almost doubling the line density while keeping most of the remaining processes and films unchanged, and provides a compelling alternative to other multipatterning integrations, which present their own sets of challenges.

The thin nature of EUV (Extreme Ultraviolet) resist has posed significant challenges for etch processes. In particular, EUV patterning combined with conventional etch approaches suffers from loss of pattern fidelity in the form of line breaks. A typical conventional etch approach prevents the etch process from having sufficient resist margin to control the trench CD (Critical Dimension), minimize the LWR (Line Width Roughness), LER (Line Edge Roughness) and reduce the T2T (Tip-to-Tip). Pre-etch deposition increases the resist budget by adding additional material to the resist layer, thus enabling the etch process to explore a wider set of process parameters to achieve better pattern fidelity. Preliminary tests with pre-etch deposition resulted in blocked isolated trenches. In order to mitigate these effects, a cyclic deposition and etch technique is proposed. With optimization of deposition and etch cycle time as well as total number of cycles, it is possible to open the underlying layers with a beneficial over etch and simultaneously keep the isolated trenches open. This study compares the impact of no pre-etch deposition, one time deposition and cyclic deposition/etch techniques on 4 aspects: resist budget, isolated trench open, LWR/LER and T2T.

The key challenge for enablement of a 2nd node of single-expose EUV patterning is understanding and mitigating the patterning-related defects that narrow the process window. Typical in-line inspection techniques, such as broadband plasma (291x) and e-beam systems, find it difficult to detect the main yield-detracting defects post-develop, and thus understanding the effects of process improvement s trategies has become more challenging. New techniques and methodologies for detection of EUV lithography defects, along with judicious process partitioning, are required to develop process solutions that improve yield. This paper will first discuss alternative techniques and methodologies for detection of lithography-related defects, such as scumming and microbridging. These strategies will then be used to gain a better understanding o f the effects of material property changes, process partitioning, and hardware improvements, ultimately correlating them directly with electrical yield detractors

In this study, the integrity and the benefits of the DSA shrink process were verified through a via-chain test structure, which was fabricated by either DSA or baseline litho/etch process for via layer formation while metal layer processes remain the same. The nearest distance between the vias in this test structure is below 60nm, therefore, the following process components were included: 1) lamella-forming BCP for forming self-aligned via (SAV), 2) EUV printed guiding pattern, and 3) PS-philic sidewall. The local CDU (LCDU) of minor axis was improved by 30% after DSA shrink process. We compared two DSA Via shrink processes and a DSA_Control process, in which guiding patterns (GP) were directly transferred to the bottom OPL without DSA shrink. The DSA_Control apparently resulted in larger CD, thus, showed much higher open current and shorted the dense via chains. The non-optimized DSA shrink process showed much broader current distribution than the improved DSA shrink process, which we attributed to distortion and dislocation of the vias and ineffective SAV. Furthermore, preliminary defectivity study of our latest DSA process showed that the primary defect mode is likely to be etch-related. The challenges, strategies applied to improve local CD uniformity and electrical current distribution, and potential adjustments were also discussed.

Initial readiness of EUV patterning has been demonstrated at the 7-nm device node with the focus now shifting to driving the 'effective' k1 factor and enabling the second generation of EUV patterning. In current EUV lithography, photoresist thicknesses <30 nm are required to meet resolution targets and mitigate pattern collapse. Etch budgets necessitate the reduction of underlayer thickness as well. Typical spin-on underlayers show high defectivity when reducing thickness to match thinner resist. Inorganic deposited underlayers are lower in defectivity and can potentially enable ultrathin EUV patterning stacks. However, poor resist-inorganic underlayer adhesion severely limits their use. Existing adhesion promotion techniques are found to be either ineffective or negatively affect the etch budget. Here, using a grafted polymer brush adhesion layer we demonstrate an ultrathin EUV patterning stack comprised of inorganic underlayer, polymer brush and resist. We show printing of sub-36 nm pitch features with good lithography process window and low defectivity on various inorganic substrates, with significant improvement over existing adhesion promotion techniques. We systematically study the effect of brush composition, molecular weight and deposition time/temperature to optimize grafting and adhesion. We also show process feasibility and extendibility through pattern transfer from the resist into typical back end stacks.

Initial readiness of EUV (extreme ultraviolet) patterning was demonstrated in 2016 with IBM Alliance's 7nm device technology. The focus has now shifted to driving the 'effective' k1 factor and enabling the second generation of EUV patterning. With the substantial cost of EUV exposure there is significant interest in extending the capability to do single exposure patterning with EUV. To enable this, emphasis must be placed on the aspect ratios, adhesion, defectivity reduction, etch selectivity, and imaging control of the whole patterning process. Innovations in resist materials and processes must be included to realize the full entitlement of EUV lithography at 0.33NA. In addition, enhancements in the patterning process to enable good defectivity, lithographic process window, and post etch pattern fidelity are also required. Through this work, the fundamental material challenges in driving down the effective k1 factor will be highlighted.

The progress of three potential DSA applications, i.e. fin formation, via shrink, and pillars, were reviewed in this paper. For fin application, in addition to pattern quality, other important considerations such as customization and design flexibility were discussed. An electrical viachain study verified the DSA rectification effect on CD distribution by showing a tighter current distribution compared to that derived from the guiding pattern direct transfer without using DSA. Finally, a structural demonstration of pillar formation highlights the importance of pattern transfer in retaining both the CD and local CDU improvement from DSA. The learning from these three case studies can provide perspectives that may not have been considered thoroughly in the past. By including more important elements during DSA process development, the DSA maturity can be further advanced and move DSA closer to HVM adoption.

Phase change material (PCM)-based memory cells have shown promise as an enabler for low power, high density memory. There is a current need to develop and improve patterning strategies to attain smaller device dimensions. In this work, two methods of patterning of PCM device structures was achieved using directed self-assembly (DSA) patterning: the formation of a high aspect ratio pore designed for atomic layer deposition (ALD) of etch damage-free PCM, and pillar formation by image reversal and plasma etch transfer into a PCM film. We show significant CD reduction (180 nm to 20 nm) of a lithographically defined hole by plasma etch shrink, DSA spin-coat and subsequent high selectivity pattern transfer. We then demonstrate structural fabrication of both DSA-defined SiN pores with ALD PCM and DSA-defined PCM pillars. Challenges to both pore and pillar fabrication are discussed.

Extreme ultraviolet lithography (EUVL) technology is one of the leading candidates for enabling the next generation devices, for 7nm node and beyond. As the technology matures, further improvement is required in the area of blanket film defectivity, pattern defectivity, CD uniformity, and LWR/LER. As EUV pitch scaling approaches sub 20 nm, new techniques and methods must be developed to reduce the overall defectivity, mitigate pattern collapse and eliminate film related defect. IBM Corporation and Tokyo Electron Limited (TEL (TM)) are continuously collaborating to develop manufacturing quality processes for EUVL.In this paper, we review key defectivity learning required to enable 7nm node and beyond technology. We will describe ongoing progress in addressing these challenges through track-based processes (coating, developer, baking), highlighting the limitations of common defect detection strategies and outlining methodologies necessary for accurate characterization and mitigation of blanket defectivity in EUV patterning stacks. We will further discuss defects related to pattern collapse and thinning of underlayer films.

The left side and right side line edge roughnesses (LER) of a line are compared for different conditions, such as through pitch, through critical dimension (CD), from horizontal to vertical line direction, from litho to etch. The investigation shows that the left and right side LER from lithography process are the same, however, the metrology can cause a 4-25% increase in the measured right side LER. The LER difference is related to the CDSEM e-beam scan direction.