In this study, the integrity and the benefits of the DSA shrink process were verified through a via-chain test structure, which was fabricated by either DSA or baseline litho/etch process for via layer formation while metal layer processes remain the same. The nearest distance between the vias in this test structure is below 60nm, therefore, the following process components were included: 1) lamella-forming BCP for forming self-aligned via (SAV), 2) EUV printed guiding pattern, and 3) PS-philic sidewall. The local CDU (LCDU) of minor axis was improved by 30% after DSA shrink process. We compared two DSA Via shrink processes and a DSA_Control process, in which guiding patterns (GP) were directly transferred to the bottom OPL without DSA shrink. The DSA_Control apparently resulted in larger CD, thus, showed much higher open current and shorted the dense via chains. The non-optimized DSA shrink process showed much broader current distribution than the improved DSA shrink process, which we attributed to distortion and dislocation of the vias and ineffective SAV. Furthermore, preliminary defectivity study of our latest DSA process showed that the primary defect mode is likely to be etch-related. The challenges, strategies applied to improve local CD uniformity and electrical current distribution, and potential adjustments were also discussed.

The progress of three potential DSA applications, i.e. fin formation, via shrink, and pillars, were reviewed in this paper. For fin application, in addition to pattern quality, other important considerations such as customization and design flexibility were discussed. An electrical viachain study verified the DSA rectification effect on CD distribution by showing a tighter current distribution compared to that derived from the guiding pattern direct transfer without using DSA. Finally, a structural demonstration of pillar formation highlights the importance of pattern transfer in retaining both the CD and local CDU improvement from DSA. The learning from these three case studies can provide perspectives that may not have been considered thoroughly in the past. By including more important elements during DSA process development, the DSA maturity can be further advanced and move DSA closer to HVM adoption.

Inpria has developed a directly patternable metal oxide hard-mask as a robust, high-resolution photoresist for EUV lithography. In this paper we demonstrate the full integration of a baseline Inpria resist into an imec N7 BEOL block mask process module. We examine in detail both the lithography and etch patterning results. By leveraging the high differential etch resistance of metal oxide photoresists, we explore opportunities for process simplification and cost reduction. We review the imaging results from the imec N7 block mask patterns and its process windows as well as routes to maximize the process latitude, underlayer integration, etch transfer, cross sections, etch equipment integration from cross metal contamination standpoint and selective resist strip process. Finally, initial results from a higher sensitivity Inpria resist are also reported. A dose to size of 19 mJ/cm2 was achieved to print pillars as small as 21nm.

Directed Self-Assembly (DSA) is being extensively evaluated for application in semiconductor process integration.(1-7) Since 2011, the number of publications on DSA at SPIE has exploded from roughly 26 to well over 80, indicating the groundswell of interest in the technology. Driving this interest are a number of attractive aspects of DSA including the ability to form both line/space and hole patterns at dimensions below 15 nm, the ability to achieve pitch multiplication to extend optical lithography, and the relatively low cost of the processes when compared with EUV or multiple patterning options.Tokyo Electron Limited has focused its efforts in scaling many laboratory demonstrations to 300 mm wafers. Additionally, we have recognized that the use of DSA requires specific design considerations to create robust layouts. To this end, we have discussed the development of a DSA ecosystem that will make DSA a viable technology for our industry, and we have partnered with numerous companies to aid in the development of the ecosystem. This presentation will focus on our continuing role in developing the equipment required for DSA implementation specifically discussing defectivity reduction on flows for making line-space and hole patterns, etch transfer of DSA patterns into substrates of interest, and integration of DSA processes into larger patterning schemes.

High-defect density in thermodynamics driven directed self-assembly (DSA) flows has been a major cause of concern for a while and several questions have been raised about the relevance of DSA in high-volume manufacturing. The major questions raised in this regard are: (1) What is the intrinsic level of DSA-induced defects? (2) Can we isolate the DSA-induced defects from the other processes-induced defects? (3) How much do the DSA materials contribute to the final defectivity and can this be controlled? (4) How can we understand the root causes of the DSA-induced defects and their kinetics of annihilation? (5) Can we have block copolymer anneal durations that are compatible with standard CMOS fabrication techniques (in the range of minutes) with low-defect levels? We address these important questions and identify the issues and the level of control needed to achieve a stable DSA defect performance. (C) 2015 Society of Photo-Optical Instrumentation Engineers (SPIE)

The patterning potential of block copolymer (BCP) materials via various directed self-assembly (DSA) schemes has been demonstrated for over a decade. We have previously reported the HONEYCOMB flow; a process flow where we utilize Extreme Ultraviolet Lithography and Oxygen plasma to guide the assembly of cylindrical phase BCPs into regular hexagonal arrays of contact holes [1, 2]. In this work we report the development of a new process flow, the CHIPS flow, where we use ArFi lithography to print guiding patterns for the chemo-epitaxial DSA of BCPs. Using this process flow we demonstrate BCP assembly into hexagonal arrays with sub-25 nm half-pitch and discuss critical steps of the process flow. Additionally, we discuss the influence of under-layer surface energy on the DSA process window and report contact hole metrology results.

High defect density in thermodynamics driven DSA flows has been a major cause of concern for a while and several questions have been raised about the relevance of DSA in high volume manufacturing. The major questions raised in this regard are: 1. What is the intrinsic level of DSA-induced defects, 2. Can we isolate the DSA-induced defects from the other processes-induced defects, 3. How much do the DSA materials contribute to the final defectivity and can this be controlled, 4. How can we understand the root causes of the DSA-induced defects, their kinetics of annihilation and finally, 5. Can we have block co-polymer anneal durations that are compatible with standard CMOS fabrication techniques (in the range of minutes) with low defect levels. This manuscript addresses these important questions and identifies the issues and the level of control needed to achieve a stable DSA defect performance.

Directed Self-Assembly (DSA) using block-copolymer (BCP) materials is considered as an alternative to Extreme Ultra-Violet (EUV) lithography for sub-14 nm half pitch technology. A BCP with natural periodicity of 28 nm was assembled on 84 nm pitch pre-pattern. 3X feature multiplication can be achieved with the chemo-epitaxy DSA flow. The BCP thickness should be thin in order to reduce the self-assembly defectivity. As a consequence, plasma etch process to transfer such thin polymer material to subsequent underlayer becomes a challenging task. The main purpose of this paper is to study the DSA pattern transfer capability of 20-25 nm BCP layer aiming at silicon fin patterning through the Si3N4 hardmask. Alternative Ar/O-2 and Ar plasmas were developed to increase the selectivity of PMIVIA to PS, and as well as reducing hydrogen passivation plasma for neutral brush layer etch. A SiCI4 encapsulation process was introduced to increase the selectivity towards Polystyrene during the Si3N4 hardmask patterning. Finally, DSA full pattern transfer to create 14 nm half-pitch line trenches with the silicon depth of 67 nm was achieved. Line width roughness (LWR) and line edge roughness (LER) of 2.56 nm and 2.64 nm respectively were achieved after PMMA removal. This DSA-based 14 nm half pitch line and space enable the building of fin structures meeting future 7 nm-technology node (N7) design rules. (C) 2014 Elsevier B.V. All rights reserved.

Directed Self-Assembly (DSA) is one of the most promising technologies for scaling feature sizes to 16 nm and below. Both line/space and hole patterns can be created with various block copolymer morphologies, and these materials allow for molecular-level control of the feature shapes—exactly the characteristics that are required for creating high fidelity lithographic patterns. Over the past five years, the industry has been addressing the technical challenges of maturing this technology by addressing concerns such as pattern defectivity, materials specifications, design layout, and tool requirements. Though the learning curve has been steep, DSA has made significant progress toward implementation in high-volume manufacturing. Tokyo Electron has been focused on the best methods of achieving high-fidelity patterns using DSA processing. Unlike other technologies where optics and photons drive the formation of patterns, DSA relies on surface interactions and polymer thermodynamics to determine the final pattern shapes. These phenomena, in turn, are controlled by the processing that occurs on clean-tracks, etchers, and cleaning systems, and so a host of new technology has been developed to facilitate DSA. In this paper we will discuss the processes and hardware that are emerging as critical enablers for DSA implementation, and we will also demonstrate the kinds of high fidelity patterns typical of mainstream DSA integrations.

An electrical test vehicle for fabricating direct self-assembly (DSA) sub-30 nm via interconnects has been fabricated employing a soft mask grapho-epitaxy contact-hole shrink. The generation of the resist pre-pattern was carried out using 193i lithography on three different stacks and the BCP assembly was evaluated with and without template affinity control on the resist pre-pattern. After DSA shrink, the holes were transferred in a 100 nm oxide for standard Tungsten metallization for electrical characterization.

Directed Self-Assembly (DSA) of Block Co-Polymers (BCP) has become an intense field of study as a potential patterning solution for future generation devices. The most critical challenges that need to be understood and controlled include pattern placement accuracy, achieving low defectivity in DSA patterns and how to make chip designs DSA-friendly. The DSA program at imec includes efforts on these three major topics. Specifically, in this paper the progress in DSA defectivity within the imec program will be discussed. In previous work, defectivity levels of similar to 560 defects/cm(2) were reported and the root causes for these defects were identified, which included particle sources, material interactions and pre-pattern imperfections. The specific efforts that have been undertaken to reduce defectivity in the line/space chemo-epitaxy DSA flow that is used for the imec defectivity studies are discussed. Specifically, control of neutral layer material and improved filtration during the block co-polymer manufacturing have enabled a significant reduction in the defect performance. In parallel, efforts have been ongoing to enhance the defect inspection capabilities and allow a high capture rate of the small defects. It is demonstrated that transfer of the polystyrene patterns into the underlying substrate is critical for detecting the DSA-relevant defect modes including microbridges and small dislocations. Such pattern transfer enhances the inspection sensitivity by similar to 10x. Further improvement through process optimization allows for substantial defectivity reduction.

Directed Self-Assembly (DSA) of Block Co-Polymers (BCP) has become an intense field of study as a potential patterning solution for future generation devices. The most critical challenges that need to be understood and controlled include pattern placement accuracy, achieving low defectivity in DSA patterns and how to make chip designs DSA-friendly. The DSA program at imec includes efforts on these three major topics. Specifically, in this paper the progress in setting up flows for templated DSA within the imec program will be discussed. A process has been implemented based on a hard mask as the template layer. In this paper primarily the impact of local pattern density and BCP film thickness on the templated DSA process are discussed. The open hole rate and the placement accuracy of BCP patterns within the template are the primary figures of merit.

Directed Self-Assembly (DSA) has become a promising alternative for generating fine lithographic patterns. Since contact holes are among the most difficult structures to resolve through traditional lithographic means, directed self-assembly applications that generate smaller contact holes are of particular interest to the industry. In this paper, DSA integrations that shrink pre-patterned contact holes were explored. The use of both block copolymers (BCPs)(1) and blended polymer systems(2) was considered. In addition, both wet(3) and dry(4) techniques were used to develop the central core out of the respective phase-separated morphologies. Finally, the hole patterns created through the various contact hole applications were transferred to substrates of interest with the goal of incorporating them into an IMEC 28 nm node via chain electrical test vehicle for direct, side-by-side comparison.