The IBM zNext's Telum II processor [1] is a full-stack overhaul of its predecessor [2], featuring a modified 5nm Samsung bulk technology [3], new IBM-created standard cell and IP libraries, and a variety of further design-technology co-optimizations (DTCO). While die size grew from $530\text{mm}^{2}$ to $600\text{mm}^{2}$ (1.13×), each chip in the dual-chip module became denser, featuring 1.3T shapes (1.25×), 43B transistors (1.38×), and 38km of wire (1.28×) across 18 BEOL layers. As IBM's first 5nm processor, Telum II was a concurrent hierarchical design effort, with libraries, IP blocks (array / regfile / analog / phy / custom), and all gate-level entities designed simultaneously. These data volume and concurrent design pressures drove a variety of abstraction, modeling, and other EDA innovations in addition to those involving power, performance, area, and reliability targets.

The POWER10™ processor designed for enterprise workloads contains 16 synchronous SMT8 cores (Fig. 2.4.1) coupled through a bi-directional high-bandwidth race-track [1] [2]. A SMT8 core with its associated cache is called a core chiplet, and a pair of core chiplets forms a 39.4mm2 design tile. Designed in a 7nm bulk technology, the 602mm2 chip (0.85× of POWER9™ [3]) has nearly 18B transistors, 110B vias and 20 miles of on-chip interconnect distributed across 18 layers of metal: 8 narrow-width layers for short range routes, 8 medium-width layers for high performance signals and two 2160nm ultra-thick metal (UTM) layers dedicated for power and global clock distribution. There are 10 input voltages as shown in Fig. 2.4.1: core/cache logic (Vdd), cache arrays (Vcs), nest logic (Vdn), two PHY voltages (Vio, Vpci), stand-by logic (Vsb), a high-precision reference voltage (Vref), DPLL voltage (VDPLL), analog circuitry voltage (VAVDD), and an interface voltage (V3P3). The C4 array contains 24477 total connections (1.25× of [3]) with 10867 power, 11879 ground and 1731 signal connections. A core and its associated L2 cache are power-gated together, while the L3 cache is power-gated independently.