As global hardware manufacturing expands and the need to meet time-to-market demands grows, companies increasingly depend on the zero-trust model to manage most of the design process for Integrated Circuits (ICs). Consequently, valuable hardware intellectual property (IP) becomes vulnerable to piracy, cloning, reverse engineering (RE), and unauthorized modifications throughout the global IC supply chain. Current security solutions are designed to safeguard the designs and protect sensitive information throughout the design flow. In this study, we present a thorough evaluation of various IP countermeasure techniques, including Logic Locking, State Space Transformation, Fine-grain Hardware Redaction, and NoC Routing Table Configuration, described in the existing literature. Inspired by cybersecurity competitions and community evaluation efforts, we designed a collaborative benchmarking initiative to evaluate these techniques on open-source benchmark designs, unveil the gaps and limitations of each technique, and discover crucial paths for future exploration. Through a retrospective analysis of this initiative, the insights we gained can significantly contribute to improving countermeasure techniques in the broad domain of hardware security and trust.

Multiple intellectual property (IP) protections have emerged to defeat security threats in integrated circuit (IC) supply chain. Among these, logic locking is regarded as a promising IP protection for its security. A state-of-the-art work uses stripped-functionality logic locking (SFLL) technique with protected input patterns (PIPs) satisfying the distance of at least 2 (Dist2) property, or D2PIPs, for ensuring resilience against both input-output (I/O)-based and structural attacks. However, this approach has research challenges in scalability, flexibility, and security, as stated and discussed in our paper. Our paper solves these challenges by (i) utilizing a satisfiability modulo theories (SMT) solver and (ii) developing a secure circuit encoding scheme. SCONE, our secure logic locking technique, combines the two methods and meets all three challenges simultaneously. Our results show that SCONE improves scalability 350x on the IBEX processor (16K gates) and remains resilient against five I/O or structural attacks.

The impact of informed high level decisions on the performance-power efficiency of semiconductors is well known. From the context of heterogeneous integration for 3D IC, new innovations are needed which close the loop from architecture to device; from multiphysics to high level abstraction; from performance to security. Such considerations will be presented.

3D ICs promise increased logic density and reduced routing congestion over conventional monolithic 2D ICs. High level synthesis (HLS) tools promise reduced design complexity by approaching the design from a higher abstraction level and allow for more optimization flexibility. We propose improving timing closure of 3D ICs by co-designing the architecture and physical design by integrating HLS and 3D IC macro placement into the same holistic loop. On average our method is able to reduce estimated total negative slack (TNS) by 62% and 92% when compared to a traditional binding and placement technique for 2D and 3D ICs respectively.

Due to the inclination towards a fab-less model of integrated circuit (IC) manufacturing, several untrusted entities get white-box access to the proprietary intellectual property (IP) blocks from diverse vendors. To this end, the untrusted entities pose security-breach threats in the form of piracy, cloning, and reverse-engineering, sometimes threatening national security. Hardware obfuscation is a prominent countermeasure against such issues. Obfuscation allows for preventing the usage of the IP blocks without authorization from the IP owners. Due to finite state machine (FSM) transformation-based hardware obfuscation, the design’s FSM gets transformed to make it difficult for an attacker to reverse-engineer the design. A secret key needs to be applied to make the FSM functional, thus preventing the usage of the IP for unintended purposes. Although several hardware obfuscation techniques have been proposed, due to the inability to analyze the techniques from the attackers’ standpoint, numerous vulnerabilities inherent to the obfuscation methods go undetected unless a true adversary discovers them. In this article, we present a collaborative approach between two entities—one acting as an attacker or red team and another as a defender or blue team , the first systematic approach to replicate the real attacker-defender scenario in the hardware security domain, which in return strengthens the FSM transformation-based obfuscation technique. The blue team transforms the underlying FSM of a gate-level netlist using state space obfuscation. The red team plays the role of an adversary or evaluator and tries to unlock the design by extracting the unlocking key or recovering the obfuscation circuitries. As the key outcome of this red team–blue team effort, a robust state space obfuscation methodology is evolved showing security promises.

Three-dimensional heterogeneous integration offers compelling opportunities to enhance the security and trust in the current semiconductor chain while new attack surfaces may emerge.

Logic locking methods such as Stripped Functionality Logic Locking (SFLL) tend to yield high overheads. SFLL only corrupts a small part of the input space by design in order to maintain good SAT resilience and in doing so selects high frequency inputs to corrupt (protect) and therefore increases locking's impact on system level error. This implies that much of the time stripped modules are doing unnecessary work while the restore units are correcting the computations. We propose taking advantage of this fact to selectively clock gate the modules when protected inputs are being processed. Under the highest possible level of attack resilience, this alone can yield up to 24.5 % dynamic power savings when protected inputs are applied to synthesized MediaBench benchmarks. We also propose a system-level design approach that utilizes the data-flow graph to also gate operations that fully depend on other gated operations. In conjunction with modifying operation binding, this increases power savings to 32.9 % under the same strict security constraints.

Logic locking techniques have been proposed to protect chip designs from malicious reverse engineering and overproduction. Stripped functionality logic locking (SFLL) has gained substantial traction as a current state of the art method, exhibiting strong resilience against a wide variety of attacks. However, secure instances of SFLL-based locking tend to have high power and area overheads, particularly in its restore units. This work presents a novel architectural approach to restore unit configuration for SFLL-like logic locking methods that treats restore units as an overhead-constrained shareable resource. We describe how resource contention caused by sharing of restore units imposes constraints on the underlying locking scheme from a graph theoretic perspective and propose both a 0-1 ILP and a heuristic clustering algorithm for finding resource-constrained shared locking configurations that satisfy these constraints. We evaluate our sharing method on SFLL-flex and find that our ILP and heuristic methods were each able to achieve a 55% and 31% reduction in power used by locked datapaths synthesized from MediaBench benchmarks while maintaining the same security and functionality compared to datapaths locked with conventional gate-level techniques.

Hardware side-channels have been exploited to leak sensitive information. With the emergence of deep learning, their hardware platforms have also been scrutinized for side-channel information leakage. It has been shown that the structure, weights, and input samples of deep neural networks (DNN) can all be the victim of reverse engineering attacks that rely on side-channel information leakage. In this paper, we survey existing work on hardware side-channel-based reverse engineering attacks on DNNs as well as the countermeasures.

The functionality of a deep learning (DL) model can be stolen via model extraction where an attacker obtains a surrogate model by utilizing the responses from a prediction API of the original model. In this work, we propose a novel watermarking technique called DynaMarks to protect the intellectual property (IP) of DL models against such model extraction attacks in a black-box setting. Unlike existing approaches, DynaMarks does not alter the training process of the original model but rather embeds watermark into a surrogate model by dynamically changing the output responses from the original model prediction API based on certain secret parameters at inference runtime. The experimental outcomes on Fashion MNIST, CIFAR-10, and ImageNet datasets demonstrate the efficacy of DynaMarks scheme to watermark surrogate models while preserving the accuracies of the original models deployed in edge devices. In addition, we also perform experiments to evaluate the robustness of DynaMarks against various watermark removal strategies, thus allowing a DL model owner to reliably prove model ownership.

Neural networks have become increasingly prevalent in many real-world applications including security critical ones. Due to the high hardware requirement and time consumption to train high-performance neural network models, users often outsource training to a machine-learning-as-a-service (MLaaS) provider. This puts the integrity of the trained model at risk. In 2017, Liu et al. found that, by mixing the training data with a few malicious samples of a certain trigger pattern, hidden functionality can be embedded in the trained network which can be evoked by the trigger pattern [33]. We refer to this kind of hidden malicious functionality as neural Trojans. In this paper, we survey a myriad of neural Trojan attack and defense techniques that have been proposed over the last few years. In a neural Trojan insertion attack, the attacker can be the MLaaS provider itself or a third party capable of adding or tampering with training data. In most research on attacks, the attacker selects the Trojan's functionality and a set of input patterns that will trigger the Trojan. Training data poisoning is the most common way to make the neural network acquire the Trojan functionality. Trojan embedding methods that modify the training algorithm or directly interfere with the neural network's execution at the binary level have also been studied. Defense techniques include detecting neural Trojans in the model and/or Trojan trigger patterns, erasing the Trojan's functionality from the neural network model, and bypassing the Trojan. It was also shown that carefully crafted neural Trojans can be used to mitigate other types of attacks. We systematize the above attack and defense approaches in this paper.

Effective vaccines are urgently needed to combat gonorrhea, a common sexually transmitted bacterial infection, for which treatment options are diminishing due to rapid emergence of antibiotic resistance. We have used a rational approach to the development of gonorrhea vaccines, and genetically engineered nanoparticles to present antigenic peptides of Neisseria gonorrhoeae, the causative agent of gonorrhea. We hypothesized that the ferritin nanocage could be used as a platform to display an ordered array of N. gonorrhoeae antigenic peptides on its surface. MtrE, the outer membrane channel of the highly conserved gonococcal MtrCDE active efflux pump, is an attractive vaccine target due to its importance in protecting N. gonorrhoeae from host innate effectors and antibiotic resistance. Using computational approaches, we designed constructs that expressed chimeric proteins of the Helicobacter pylori ferritin and antigenic peptides that correspond to the two surface‐exposed loops of N. gonorrhoeae MtrE. The peptides were inserted at the N terminus or in a surface‐exposed ferritin loop between helices αA and αB. Crystal structures of the chimeric proteins revealed that the proteins assembled correctly into a 24‐mer nanocage structure. Although the inserted N. gonorrhoeae peptides were disordered, it was clear that they were displayed on the nanocage surface, but with multiple conformations. Our results confirmed that the ferritin nanoparticle is a robust platform to present antigenic peptides and therefore an ideal system for rational design of immunogens.

The PhoP-PhoR two-component system is essential for the virulence of Mycobacterium tuberculosis (Mtb) and therefore represents a potential target for developing novel antituberculosis therapies. However, little is known about the mechanism by which this two-component system regulates the virulence. In this study, we demonstrated that a phoR mutant Mtb strain has phenotypes similar to those of a phoP mutant, suggesting that PhoP and PhoR work in the same pathway to regulate Mtb virulence. We determined the structure of the dimerization and histidine phosphotransfer (DHp) domain of PhoR to a 1.9 Å resolution. The structure revealed that the DHp domain is a dimer. Each subunit consists of two antiparallel α helices connected by a loop of five residues. The two subunits of the dimer fold into a four-helical bundle with a continuous hydrophobic core. The topology of the four-helical bundle is identical to the histidine kinases that are known to have a cis-autophosphorylation mechanism, suggesting that PhoR is likely to autophosphorylate in cis. The dimer is asymmetric, with one subunit having a greater bending angle than the other at the highly conserved proline residue five-residues downstream of the phosphorylation site histidine. This structural asymmetry of the dimer suggests the flexibility of the PhoR DHp domain, which is likely to be important for the signal transduction mechanism in controlling the autophosphorylation and phosphotransfer reactions and communicating with the upstream structure.

Intracranial/intracerebral hemorrhage (ICH) is a leading cause of death and disability in people with traumatic brain injury (TBI) and stroke. No proven drug is available for ICH. Panax notoginseng (total saponin extraction, PNS) is one of the most valuable herb medicines for stroke and cerebralvascular disorders in China. We searched for randomized controlled clinical trials (RCTs) involving PNS injection to treat cerebral hemorrhage for meta-analysis from various databases including the Chinese Stroke Trials Register, the trials register of the Cochrane Complementary Medicine Field, the Cochrane Central Register of Controlled Trials, MEDLINE, Chinese BioMedical disk, and China Doctorate/Master Dissertations Databases. The quality of the eligible trials was assessed by Jadad's scale. Twenty (20) of the 24 identified randomized controlled trials matched the inclusive criteria including 984 ICH patients with PNS injection and 907 ICH patients with current treatment (CT). Compared to the CT groups, PNS-treated patients showed better outcomes in the effectiveness rate (ER), neurological deficit score, intracranial hematoma volume, intracerebral edema volume, Barthel index, the number of patients died, and incidence of adverse events. Conclusion: PNS injection is superior to CT for acute ICH. A review of the literature shows that PNS may exert multiple protective mechanisms against ICH-induced brain damage including hemostasis, anti-coagulation, anti-thromboembolism, cerebral vasodilation, invigorated blood dynamics, anti-inflammation, antioxidation, and anti-hyperglycemic effects. Since vitamin C and other brain cell activators (BCA) that are not considered common practice were also used as parts of the CT in several trials, potential PNS and BCA interactions could exist that may have made the effect of PNS therapy less or more impressive than by PNS therapy alone. Future PNS trials with and without the inclusion of such controversial BCAs as part of the CT could clarify the situation. As PNS has a long clinical track record in Asia, it could potentially become a therapy option to treat ICH in the US and Europe. Further clinical trials with better experimental design could determine the long-term effects of PNS treatment for TB I and stroke.