This paper introduces a novel design automation approach for securing Systems-on-Chip (SoCs) by natively integrating security as a primary optimization objective. Unlike existing design automation solutions that typically explore implementations for specific vulnerabilities, our method utilizes a purpose-built security metric specifically tailored for SoCs. Our optimization algorithm accepts a system specification (either as an application or an abstract SoC description) and generates a secured SoC architecture. This architecture enhances the regular SoC with an optimized security component. Optimization goals include critical metrics such as security, area, power, and latency, which are quantified as system risk. As a proof of concept, the proposed DSE of security tested three distinct security optimization strategies on a single system architecture: unrestricted resource and power utilization, restricted resource utilization, and restricted power utilization. The optimizer effectively returns all valid solutions that adhere to the user’s defined risk constraints, clearly showcasing the inherent trade-offs between optimized system risk, Look-Up Table (LUT) utilization, and power consumption. The results demonstrate how designers can leverage this tool to identify optimal security and anomaly detection solutions tailored to their specific system architectures. For instance, while the most secure solution might demand thousands of LUTs, our tool facilitates balanced decision-making by considering security alongside resource, power, and latency constraints. This allows designers to incorporate security directly into the design process.
Matrix multiplication underpins a wide range of compute-intensive workloads, from image processing to deep learning inference. This work presents a novel hardware accelerator architecture that combines Strassen’s algorithm, systolic array optimizations, and approximate computing to enhance efficiency in area and power. At the leaf recursion level of Strassen’s algorithm, conventional exact multipliers (EMs) are selectively replaced with approximate multipliers (AMs). To preserve accuracy in critical paths, time-shared EMs are retained, balancing efficiency with correctness. The accelerator is built around multiple $64 \times 64$ systolic arrays comprising 4096 processing elements (PEs). Each PE dynamically selects from ten available AMs, producing a vast discrete design space. To navigate this combinatorial complexity, we propose a Variational Autoencoder (VAE) that compresses PE-level approximation configurations into a compact latent space. A multi-objective evolutionary algorithm (MOEA) then searches this space to optimize hardware-level metrics (area, power, delay) alongside application-level performance indicators such as SSIM, PSNR, and classification accuracy. Our design maintains numerical stability across recursive layers, ensuring the practical realization of Strassen’s asymptotic advantage over conventional multiplication. Through MOEA-driven exploration, we identified accelerator designs that reduce hardware footprint by up to 33% and improve power-delay product by 21%, with only a 0.9% drop in CNN classification accuracy. By decoding latent codes back to full PE configurations, the VAE enables fast and high-quality exploration, generating a composite Pareto frontier of optimized designs. Overall, this framework demonstrates effective co-optimization of hardware efficiency and application accuracy, providing low-cost, high-performance matrix multiplication tailored for approximate computing workloads.
The growing need for additional primary memory capacity in data centers and exascale computing is driving the integration of DRAM and NVMs, which utilizes the advantages of both memory types and lessens the drawbacks of these memory types. To maximize main memory capacity and ensure efficient use of PCM, migrating write-intensive pages to DRAM enables better overall performance. Accurately identifying migration candidates is non-trivial: static threshold-based schemes either move pages at fixed intervals or, whenever write counts cross a preset cutoff, often misplace hot data. More sophisticated machine-intelligent methods (e.g., LSTM- or Attention-based predictors, Deep RL) can adapt to complex access patterns but incur prohibitive training and inference overheads for on-chip deployment. In this paper, we present a lightweight, online RL-based migration scheme: PEARL. PEARL is a tabular Q-learning/banditstyle algorithm that maintains per-page “confidence” (Q-value), updates based on the access patterns, and drives promotion to DRAM or eviction to NVM. The proposed method is validated against state-of-the-art threshold-based migration techniques using SPEC 2017 benchmark suite applications. The method improves performance by $6 \%$ and reduces total energy consumption by $16 \%$, demonstrating a practical path to higher performance and greater write endurance.
In this work, we first implement a computational statistics framework for the design optimization of common-drain complementary field-effect transistor (CFET). By using numerical device simulations in combination with statistical design of experiments (DOE) methodology-specifically the central composite design (CCD)-we construct second-order response surface model (RSM) for all targeted electrical characteristics of CFET. Both the adequacy and accuracy of each RSM are verified through normal residual probability plots and residual-sum-of-squares analysis. These validated models are further employed to optimize CFET performance for its circuit applications. By jointly considering threshold voltage, off-state current, on-state current, subthreshold swing, and drain-induced barrier lowering, the structural parameters of the CFET are tuned such that the predicted electrical characteristics approach the desired targets more effectively than that of the nominal design. Moreover, Device simulations of the optimized structures of CFET show strong agreement with the RSM-predicted values, confirming the robustness and accuracy of the developed models. This study represents the DOE-based RSM optimization framework for CFETs, and the formulated equations show highly predictive fidelity, providing a compelling and practical guideline for CFET design prior to high-volume manufacturing.
An industry-strength hybrid optimization approach, involving derivative-free global search followed by derivative-free local refinement, is proposed to solve the multi-dimensional problem of compact model parameter extraction and reduce its multi-objective nature while retaining the original device physical formulations. An intelligent transition method is employed to combine Differential Evolution and Nelder-Mead algorithms from a curated selection of machine learning-driven optimizer candidates, achieving better-fitting performance in various operating regions for the first time. Extraction results for compact models such as ASM-HEMT with 35 parameters and BSIM4 with 29 parameters in 3 steps show that a best-fit error of less than $0.2 \%$ is achieved with much less automatic extraction time of 1800 seconds compared to hours of global search alone and weeks of traditional manual parameter tuning. A new cost function is introduced to reduce sensitivity to outliers and introduce region-appropriate automatic weights while preserving device physical formulations. This approach helps reduce total optimization time by a factor of at least 2 X compared to global optimization alone and reduces dependency on modeling know-how.
As specialized machine learning (ML) accelerators become increasingly prevalent in edge devices, new yet significant security challenges emerge due to the increased risk of adversaries gaining physical access to the hardware. This ease of access can enable reverse engineering, model extraction, or hardware-level attacks that are not feasible in cloud or data center environments. Edge devices, in particular, often process sensitive data such as biometric features or medical images. In this work, we present an electromagnetic (EM) side-channel attack targeting the Google Coral Edge TPU, a commercial lowpower neural network inference engine. We develop a dedicated EM measurement setup to capture high-resolution leakage signals from the device during neural network inference. Leveraging this setup, we perform an input recovery attack that combines profiled side-channel analysis with a generative neural network and a custom-designed loss function. Our method is able to reconstruct images processed on different architectures deployed on the Edge TPU, demonstrating that sensitive user input data can be recovered from physical leakage. This finding highlights the significant privacy risks associated with deploying ML models on edge devices without adequate side-channel resistance.
This work evaluates the on-chip variability of the Anderson PUF by instantiating 128 designs on a Nexys A7 FPGA and collecting 100 UART samples per configuration using a lightweight Python automation script. MUX distance (MDIST) and flip-flop (FF) placement are varied to assess placement sensitivity, uniformity, and uniqueness. Preliminary results show wide intra-chip uniformity variation with no consistent trend; MDIST $=2$ yields the most balanced outputs, while larger distances produce strong skew. These findings highlight the impact of routing and placement and provide guidance for reliable FPGA-based implementations.
In this paper, we present an ESD characterization and sensitivity analysis methodology using a Technology Computer-Aided Design (TCAD)-based gate-grounded NMOS (GGNMOS) digital twin. First, the virtual GGNMOS device is created by simulating the fabrication process of a $0.35 \mu \mathrm{~m}$ CMOS technology. The digital twin is then calibrated to a known device by matching the transmission line pulse (TLP) IV curves. Second, a one-at-a-time (OAT) sensitivity analysis is performed for various device/process parameters. In particular, the impact of device/process parameters on the trigger point, breakdown point, and on-resistance was quantified. Statistical box plots are used to interpret the results of the sensitivity analysis. Finally, the OAT analysis is leveraged to generate a targeted labeled dataset that includes all the failure modes with respect to the ESD design window. This proposed platform opens the door to applying machine learning (ML) to the design and refinement of the ESD protection circuit/window while accounting for process variation.
Finite State Machines (FSMs) are a core abstraction for modeling digital systems, control logic, and reactive behaviors. Automating FSM state and transition identification is therefore critical for computer-aided design (CAD) tools. While multi-modal large language models (MLLMs) have shown promise in design automation, FSM diagrams are often not directly interpretable by these models, resulting in errors in control synthesis and HDL generation. This paper presents FSMVision, a multi-modal artificial intelligence (AI) framework that extracts complete FSM semantics directly from diagrams. By integrating visual parsing, spatial reasoning, and language grounding, FSMVision accurately identifies states, transitions, and conditions for design automation. Experiments demonstrate 99.00% state detection and 99.01% transition detection accuracy across diverse FSM diagrams of varying complexity. FSMVision surpasses existing MLLM-based baselines, achieving superior structural and semantic fidelity, and enables direct translation of FSM diagrams into executable implementations, advancing AI-driven design and control automation.
As the energy consumed in manufacturing and operating information and computing technologies (ICT) accounts for an increasing percentage of worldwide carbon emissions, there is a growing urgency to address the carbon footprint generated by the computing infrastructure. Although the world has witnessed a drastic increase in computing performance for large neural network models with the use of more transistors and miniaturized dimensions, the advanced fabrication of these highend integrated circuits incurs more energy and environmental costs than use-phase costs, making it a critical sustainability challenge. Emerging technology such as silicon photonics is being proposed for both communication and computation in neural network accelerators due to better performance-perwatt and higher bandwidth density compared to traditional electronics. In this paper, we conduct a comprehensive carbon emission analysis on hardware accelerators for neural network applications considering both traditional electrical and emerging silicon photonics technology. We propose a carbon-emissionbased sustainability model that considers photonic devices and interconnects. The model accounts for both the carbon emissions due to manufacturing as well as the lifetime operation of the devices. We compare three designs - electrical, photonics, and hybrid architectures - that explore the trade-offs between computational performance and environmental costs for different neural network models. With our proposed sustainability-aware design, we demonstrate that utilizing silicon photonics improves computational performance along with superior environmental sustainability.
The increasing threat posed by quantum computers to classical cryptographic systems necessitates the adoption of post-quantum cryptographic (PQC) algorithms. CRYSTALS-Dilithium, a lattice-based digital signature scheme standardized by NIST, relies heavily on efficient polynomial multiplication using the number theoretic transform (NTT). This work presents an FPGA implementation of Dilithium-NTT, optimizing both the modular multiplication unit and the memory access scheme. The modular multiplier leverages the data in LUTs and an accelerated K-RED algorithm, achieving high performance with low resource overhead (111 LUTs, 137 FFs, and 02 DSPs at a frequency of 613 MHz). The proposed NTT architecture employs a dual ping-pong memory access scheme, eliminating the need for BRAMs while utilizing LUTs for intermediate data storage. Implemented on the Xilinx Zynq UltraScale+ ZCU104 and Artix-7 AC701 FPGA prototyping platforms, the design achieves a $14 \%$ improvement in the area-time product compared to state-of-the-art solutions, with $12 \%$ lower LUT usage with an advantage of $6 \%$ higher operating frequency. These results demonstrate a scalable and resource-efficient approach for the deployment of PQC primitives in constrained hardware environments.
The rapid deployment of artificial intelligence (AI) systems has introduced a new class of security vulnerabilities rooted in hardware behavior. Unlike software-only threats, hardware-oriented attacks exploit physical effects and micro-architectural characteristics of the computing substrate, allowing adversaries to induce faults, extract sensitive information, or stealthily manipulate inference outcomes. Recent studies show that deep neural network (DNN) accelerators are particularly susceptible to such attacks, including selective bit-flip fault injection via Rowhammer or voltage glitching, side-channel leakage through power and electromagnetic emanations, and hardware Trojan insertion during fabrication or third-party intellectual property (IP) integration. Even a small number of hardware modifications can result in severe accuracy degradation, targeted misclassification, or denial-of-service. In this paper, we cover the evolving landscape of hardware-based attack vectors targeting AI accelerators (e.g., DNNs) and the corresponding defense methods. We systematically categorize fault-injection, side-channel, and hardware Trojan attacks; examine their threat models and practical impact on DNN inference; and review existing protection techniques. We emphasize lightweight defenses for resource-constrained edge platforms, highlighting AI Performance Counters as passive, low-overhead observability primitives that capture execution-level signatures of neural workloads for runtime anomaly detection. We outline open challenges and future research directions toward resilient and trustworthy AI hardware systems.
Spectre attacks exploit speculative execution to leak sensitive data, especially in Artificial Intelligence (AI) workloads, through microarchitectural side channels, posing persistent challenges to modern processors. While advanced defenses like adaptive contention monitoring and resource isolation offer strong protection, they often require costly hardware redesigns. To provide a practical alternative, we introduce Contention Balancer, a fine-grained, software-level mitigation that leverages SpecScope’s automated gadget identification and contention mapping. By injecting carefully selected balancing instructions into speculative paths, Contention Balancer equalizes execution characteristics between transient and non-transient paths, effectively masking contentionbased side-channel signals without altering program behavior. This approach delivers immediate, low-overhead protection against Spectre vulnerabilities, offering a deployable and cost-effective solution for securing computing systems in the AI era.
Computing-in-memory (CIM) architectures have successfully enhanced convolutional neural network (CNN) performance, but the automation of high-performance CIM-based transformer accelerators is still challenging. Specifically, the design space of hardware design and mapping is extremely large due to the complex model structure and data flow. To address this problem, we propose Harmony, a hardware and mapping co-exploration framework to optimize the hybrid CIM-based vision transformer accelerator. We define a universal design space representation for implementing vision transformers in CIM-based accelerators that support hybrid and heterogeneous features. The corresponding design space comprises the hardware configuration of CIM macros and their spatial mapping scheme. Furthermore, we propose the knowledge-guided grid search (KGGS) algorithm and improved genetic algorithm (IGA) to boost exploration efficiency. The orthogonal experiment and dominance analysis of KGGS could obtain the exploration probabilities of different parameters and ensure its stability, while the unique order crossover and swapping mutation of IGA could retain relative order to avoid legalization processes during the iteration. Performance experimental results show that Harmony achieves $48 \%$ area reduction, $13 \%$ latency reduction, $32 \%$ energy reduction, and $1.27 \times$ energy efficiency on average compared with the baseline. The accuracy experiment demonstrates that our hybrid architecture achieves a trade-off between accuracy and performance compared with all-SRAM CIM-based accelerators.
Reconfigurable Approximate Computing (RAC) is emerging as a crucial approach for designing adaptive digital systems, particularly as modern AI models require dynamic error tolerance during runtime. To address this need, there is a requirement for a runtime-reconfigurable approximate circuit design methodology that enables variation in error and power levels. Some prior work has proposed dynamic approximate circuits that accept error levels as constraints and then optimize power consumption for each power level. This work explores and compares various Multi-Objective Evolutionary Algorithms (MOEAs) that modify circuit netlists to generate Pareto-optimal solutions, strategically replacing wires with control gates to achieve significant power savings. While technology-independent, our method was validated on various benchmarks using the Predictive FinFET ASAP $7 n m$ Regular $V_{t}$ Typical Corner PDK. This paper demonstrates that our proposed method enables more flexible and informed configuration selection by leveraging the error-power trade-off, ultimately leading to more efficient design choices from Pareto-front solutions. The framework is released as an open-source tool for the VLSI research community for further adoption.
Edge inference, particularly for AI-driven mobile applications, faces significant hurdles due to the resource constraints of internet-of-things (IoT). Deploying large and complex deep neural networks (DNNs) in such systems leads to high power consumption, increased latency, and memory limitations, hindering real-time performance and scalability. To address these challenges, this paper presents two approaches to optimize DNNs for efficient edge computing in IoT, focusing on radio modulation identification. First, a lightweight convolutional neural network (CNN) is tailored to simplify the inference model and reduce the resource constraints in edgeenabled devices. Specifically, by linearizing pooling layers as well as integrating convolutional and pooling operations into a single matrix suitable for hardware implementation, our lightweight CNN achieves significant parameter reduction and faster inference. Secondly, an echo state network (ESN), a form of reservoir computing, is introduced to address the limitations of online learning when processing dynamic data streams. To be specific, by utilizing an untrained reservoir layer for high-dimensional input encoding, ESN reduces computational complexity and energy use when solely training its readout layer. The advantages of ESN over alternative methods are highlighted, paving the way for efficient radio modulation identification systems at the edge by avoiding data scarcity and the vanishing gradient problem.
Power estimation is crucial in VLSI design, enabling early evaluation of energy efficiency. Traditional gatelevel simulation-based methods offer higher accuracy but are time-consuming, while RTL simulation-based methods are faster but less precise. Recently, machine learning-based methods have emerged as a promising solution, achieving a balance between speed and accuracy. This paper presents a GNN-based framework for gate-level average power estimation, comprising two key steps: (1) signal activity prediction and (2) average power calculation. The first step improves upon an existing GNN-based switching activity predictor by integrating more circuit information and refining feature representations, leading to significant accuracy gains. The predicted signal activities are then formatted as a Switching Activity Interchange Format file, which is used by a commercial power analysis tool to compute the average total power, including dynamic and static contributions. Experimental results demonstrate that our signal activity prediction achieves an RMSE of 0.02991 on ISCAS’85 benchmarks with random patterns, a 0.05221 improvement over prior work, and 0.01852 on industrial designs with real patterns. Furthermore, our average power estimation achieves errors of $\mathbf{1. 3 3 \%}$ on ISCAS’85 benchmarks with random patterns and 5.62% on industry designs with real patterns.
Real-time semantic understanding for drone swarms demands robust multi-object perception and high-level reasoning under tight size, weight, power, and bandwidth constraints. Existing approaches either offload computation to cloud or ground stations, achieving rich semantics at the cost of latency and fragile links, or rely on lightweight on-board trackers that produce only low-level bounding boxes and trajectories. We bridge this gap with an edge-native pixels-to-semantics pipeline that combines a streaming FPGA front-end with an on-device large language model (LLM). A near-sensor FPGA accelerator on a Zynq UltraScale+ MPSoC performs real-time multi-object tracking and emits a compact structured state with stable IDs, kinematic summaries, and interaction cues; a fine-tuned, quantized LLM on the on-board ARM cores consumes this state to infer swarmlevel behaviors, inter-object relations, and potential risks without processing raw pixels or relying on network connectivity. On a KV260 platform, the pipeline achieves an end-to-end visual latency of 66.7 ms per frame at $320 \times 240$, operates at approximately 2.9 W, and uses less than 2% of the device’s LUT/FF resources and a single BRAM block. We compare our system against hybrid and full-offloading architectures in latency, bandwidth, and power, and against representative FPGA-based visual frontends in hardware footprint. Finally, we evaluate the on-board LLM against an online ChatGPT 5.1 Auto baseline on a real multi-UAV rounding sequence, showing that the self-deployed model achieves zero error in corrected-count and mission-type prediction while the general-purpose model exhibits substantial errors, yielding a practical low-SWaP solution for semantic scene understanding in drone swarms.
Fixed-model deployment in object detection wastes computation on easy frames and degrades performance on challenging ones. We present an uncertainty-guided adaptive model hopping system that dynamically switches among five YOLOv8 models (3.2M-68.2M parameters) based on per-frame tracking difficulty. Unlike prior approaches that rely on systemlevel indicators such as CPU load or bandwidth, the method uses detector confidence and lightweight uncertainty signals to estimate frame complexity and allocate compute accordingly. High-confidence frames are processed with lightweight models, while low-confidence or high-uncertainty detections trigger transitions to higher-capacity models. Bidirectional switching with hysteresis prevents oscillation and supports escalation under challenging conditions as well as de-escalation when confidence recovers. Experiments on seven MOT17 sequences (4,746 frames) demonstrate a 58.2% reduction in computation relative to always using YOLOv8-XLarge while preserving $99.6 \%$ tracking success. The system achieves 28 FPS on an Intel NUC 14 Pro using OpenVINO, demonstrating practical real-time edge deployment without model retraining or architectural modification.
Test engineers developing validation programs for Analog-to-Digital Converters (ADCs) often lack early access to detailed circuit models or silicon, requiring reliable behavioral models that reflect specification-level error metrics. Existing approaches frequently approximate non-idealities such as Integral Non-Linearity (INL), offset, and gain in a statistical manner, leading to inaccuracies which undermine test development. This work introduces an algorithm for the creation of behavioral ADC models that enables precise, specification-driven control of static ADC errors - particularly enforcing a defined maximum INL - while preserving configured offset and gain values. Unlike statistical approaches, the algorithm deterministically generates compliant profiles and supports consistent instantiation across different bit resolutions. Simulations show accuracy and fast runtime via a one-time precomputation strategy, making the approach suitable for early-stage test development, virtual validation of test programs, and potentially large-scale SoC simulations.
