Quantum error correction is essential for building scalable quantum computers. Within the stabilizer formalism, the Calderbank-Shor-Steane framework constructs quantum codes from pairs of classical linear codes. A distinctive feature in this setting is degeneracy, where multiple equivalent error estimates exist-a phenomenon that has no classical counterpart, and the lack of a meaningful classical coding-theoretic interpretation of which has remained a gap in the literature. In this paper, we demonstrate that degeneracy is closely related to the classical operation of shortening of a linear block code. Interestingly, the shortening here takes place at the decoder rather than at the encoder. Leveraging this insight, we present a parallel decoding scheme for quantum low-density parity-check codes, which we term impulse decoding, that significantly outperforms belief propagation with ordered statistics decoding, as well as several other existing techniques, under both code-capacity and circuit-level noise, with significantly lesser complexity. We then present another algorithm based on decoding of residual errors, which when combined with impulse decoding achieves further performance improvement under circuit-level noise.

Quantum error correction (QEC) is critical for practical realization of fault-tolerant quantum computing, and recently proposed families of quantum low-density parity-check (QLDPC) code are prime candidates for advanced QEC hardware architectures and implementations. This paper focuses on the finite-length QLDPC code design criteria, specifically aimed at constructing degenerate quasi-cyclic symmetric lifted-product (LP-QLDPC) codes. We describe the necessary conditions such that the designed LP-QLDPC codes are guaranteed to have a minimum distance strictly greater than the minimum weight stabilizer generators, ensuring superior error correction performance on quantum channels. The focus is on LP-QLDPC codes built from quasi-cyclic base codes belonging to the class of type-I protographs, and the necessary constraints are efficiently expressed in terms of the row and column indices of the base code. Specifically, we characterize the combinatorial constraints on the classical quasi-cyclic base matrices that guarantee construction of degenerate LP-QLDPC codes. Minimal examples and illustrations are provided to demonstrate the usefulness and effectiveness of the code construction approach. The row and column partition constraints derived in the paper simplify the design of degenerate LP-QLDPC codes and can be incorporated into existing classical and quantum code design approaches.

This paper proposes a new finite precision iterative decoder for low-density parity-check (LDPC) codes. The proposed decoder, named Sign-Preserving Min-Sum (SP-MS), significantly improves the decoding performance compared to the classical Offset Min-Sum (OMS) decoder when messages are quantized on $q=2$ , 3, or 4 bits. The particularity of the SP-MS decoder is that messages cannot take the 0 value, and can fully benefit from the $q$ bits of precision. The optimization of the SP-MS decoder is investigated in the asymptotic limit of the code length using density evolution (DE). Our study shows that 3-bit SP-MS decoders can achieve the same error-correcting performance as 5-bit OMS decoders, and 2-bit SP-MS decoders outperform 3-bit OMS decoders. The finite-length simulations confirm the conclusions of the DE analysis for several LDPC codes. Our SP-MS decoder shows a signal-to-noise ratio (SNR) gain up to 0.43 dB, with a memory/wire reduction of up to 40%, compared to the OMS decoder. Moreover, the SP-MS decoder converges faster and uses fewer iterations than the OMS decoder, with an improvement of up to 83.3% of the average decoding throughput. On an FPGA, the SP-MS decoder reduces resource utilization by up to 56% compared to the OMS decoder.

Low-density parity-check (LDPC) code as a very promising error-correction code has been adopted as the channel coding scheme in the fifth-generation (5G) new radio. However, it is very challenging to design a high-performance decoder for 5G LDPC codes because their inherent numerous degree-1 variable-nodes are very prone to be erroneous. In this article, the problem is solved gracefully by developing a low-complexity check-node update function, greatly improving the reliability of check-to-variable messages. By further incorporating the proposed column degree adaptation strategy, our decoder could offer a 0.4dB performance gain over the existing ones. In addition, this article presents an efficient 5G LDPC decoder architecture. Benefiting the specific structure of 5G LDPC codes, layer merging, split storage method, and selective-shift structure are introduced to facilitate a significant reduction of decoding delay and area consumption. Implementation result on 90-nm CMOS technology demonstrates that the proposed decoder architecture yields an impressive improvement in throughput-to-area ratio, achieving up to 173.3% compared to conventional design.

In this paper, we present a computationally efficient method for estimating error floors of low-density parity-check (LDPC) codes over the binary symmetric channel (BSC) without any prior knowledge of its trapping sets (TSs). Given the Tanner graph G of a code, and the decoding algorithm V, the method starts from a list of short cycles in G, and expands each cycle by including its sufficiently large neighborhood in G. Variable nodes of the expanded sub-graphs EXP are then corrupted exhaustively by all possible error patterns, and decoded by V operating on EXP. Union of support of the error patterns for which V fails on each EXP defines a subset of variable nodes that is a TS. The knowledge of the minimal error patterns and their strengths in each TSs is used to compute an estimation of the frame error rate. This estimation represents the contribution of error events localized on TSs, and therefore serves as an accurate estimation of the error floor performance of V at low BSC cross-over probabilities. We also discuss trade-offs between accuracy and computational complexity. Our analysis shows that in some cases the proposed method provides a million-fold improvement in computational complexity over standard Monte-Carlo simulation.

In this presentation, we propose an LDPC solution for emerging non volatile memories, such as 3D Xpoint or RRAMs. We optimize the quasi-cyclic LDPC so that the erasures coming from die read failures can be easily recovered before decoding. We then introduce a new Erasure-FAID decoder, with the feature of using different update rules for the erased and non-erased bits. Together with using the concept of decoder diversity, we show that our new decoder gives impressive gains compared to the legacy Reed-Solomon solution.

Systematic Polar codes offers the same frameerror-rate (FER) performance compared with non-systematic Polar codes in almost communications channels although they have advantages in bit-error-rate (BER) performance. In recent papers, NAND flash memories have been confirmed for its asymmetric error characteristic, and the 2-Beta-Binomial (2-BBM) error model has been presented to provide accurate simulation of observed errors in multi-level cell (MLC) flash memories under different Program/Erase cycles. In this paper, we propose concatenating a distribution generator (DG) which can modify user data distribution with systematic Polar encoder (SPE) for MLC NAND Flash memory. The proposed method shows remarkable improvement in FER performances compared with non-systematic candidates, especially in lower pages of the two memory vendors.

We propose in this paper a new approach of applying the Non-Surjective Finite Alphabet Iterative Decoder (NS-FAID) for the Low-Density Parity-Check (LDPC) decoding. Differently from the NS-FAID which applies a fixed nonlinear function by using a fixed Look-Up-Table (LUT) on the variable node messages, the proposed method, called Probabilistic FAID (PFAID), uses more than one LUT in a probabilistic way. By using the density evolution, we show that this method provides a significant improvement in performance compared to the NS-FAID and the traditional MS. The advantage of PFAID is shown by the fact that, a PFAID with low message quantization level can reach or even surpass the performance of the higher level quantization MS decoder. Furthermore, we show that PFAID can be efficiently implemented with no hardware overhead compared to Min-Sum (MS) or NS-FAID with the same message quantization level. The hardware complexity analysis and decoding simulation performance are provided as superiority evidences of PFAID over the referenced benchmarks.

This paper presents an Enhanced Offset Min-Sum (EOMS) decoder for Low-Density Parity-Check (LDPC) codes used in the 5th generation (5G) mobile communications. It is observed that a significant part of Variable Nodes (VNs) in the 5G LDPC codes are with degree-1 and are very sensitive to be erroneous, leading to the fact that the decoding performance is generally reduced. In the EOMS decoding, the core check nodes (CN) and extension CNs are processed with different update rules. A new CN -update criterion is also proposed by making use of the third minimum value. As a result, the offset factors are adaptively selected and the error probability of degree-1 VNs is significantly reduced. Simulation results show that the proposed EOMS decoder offers a much better error-correction performance than the state-of-the-art benchmarks for several 5G LDPC codes with a negligible complexity overhead.

This paper presents an Enhanced Offset Min-Sum (EOMS) decoder for Low-Density Parity-Check (LDPC) codes used in the 5th generation (5G) mobile communications. It is observed that a significant part of Variable Nodes (VNs) in the 5G LDPC codes are with degree-1 and are very sensitive to be erroneous, leading to the fact that the decoding performance is generally reduced. In the EOMS decoding, the core check nodes (CN) and extension CNs are processed with different update rules. A new CN -update criterion is also proposed by making use of the third minimum value. As a result, the offset factors are adaptively selected and the error probability of degree-1 VNs is significantly reduced. Simulation results show that the proposed EOMS decoder offers a much better error-correction performance than the state-of-the-art benchmarks for several 5G LDPC codes with a negligible complexity overhead.

Since the degree-1 variable nodes (VNs) in the low-density parity-check (LDPC) codes for the 5th generation (5G) mobile communications are very sensitive to be erroneous, the quantized min-sum (QMS) and offset min-sum (QOMS) decodings suffer from poor error-correction performance due to the imprecise estimation of the check-to-variable (C2V) message magnitudes. For this reason, this paper proposes a decomposition mapping based quantized belief propagation (DM-QBP) decoding for 5G LDPC codes. In order to reduce the computation complexity, the check node (CN) update function is realized by look-up tables (LUTs). Furthermore, a decomposition method is presented to eliminate the high memory cost of using large tables without performance loss. Therefore, the CN update function can be implemented based only on simple mappings and fixed-point additions. Simulation results show that, the DM-QBP decoder considerably outperforms the state-of-the-art ones for several 5G LDPC codes. With a small number of quantization bits, its performance is even better than the floating-point OMS decoding in some cases.

In this paper, a method to approximate the second minimum required in the computation of the check node update of an LDPC decoder based on min-sum algorithm is presented. The proposed approximation compensates the performance degradation caused by the utilization of a first minimum and pseudo-second minimum finder instead of a true two minimum finder in the min-sum algorithm and improves the BER performance of high-rate LDPC codes in the error floor region. This approach applied to a complete decoder reduces the critical path and the area with independence of the selected architecture. Therefore, this method increases the maximum throughput achieved by the decoder and its area-throughput efficiency. The increase in efficiency is proportional to the degree of the check node, so the higher the code rate is, the higher the improvement in area and speed is.

This paper presents an adaptation of the Min-Sum decoders for the Low-Density Parity-Check (LDPC) used in the enhanced mobile broadband (eMBB) scenario in the 5th generation mobile networks (5G). Starting from the structure of the proposed LDPC codes for 5G where a significant part of the Variable Nodes (VNs) is with degree-1 and is sensitively to be erroneous in the traditional Offset Min-Sum decoder, we adapt the Min-Sum decoding principle to decode these 5G LDPC codes, targeting to improve the error correction performance. The proposed decoder, named Adapted Min-Sum (AMS), processes the core and the extension parts of the code differently using different offset factors. By doing that, the error probability of degree-1 VN is significantly depressed. We show through the simulation performance that the proposed decoder, with small number of quantization bits, can even surpass the floating-point counterpart and approaches the performance of the Sum-Product decoder for several 5G LDPC code lengths and code rates, with negligible additional complexity.

This paper proposes a holistic approach that addresses both the message mapping in memory banks and the pipeline-related data hazards in low-density parity-check (LDPC) decoders. We consider a layered hardware architecture using single read/single write port memory banks. The throughput of such an architecture is limited by memory access conflicts, due to improper message mapping in the memory banks, and by pipeline data hazards, due to delayed update effect. We solve these issues hy: 1) a residue-based layered scheduling that reduces the pipeline related hazards and 2) off-line algorithms for optimizing the message mapping in memory banks and the message read access scheduling. Our estimates for different LDPC codes indicate that the hardware usage efficiency of our layered decoder is improved by 3%-49% when only the off-line algorithms are employed and by 16%-57% when both the residue-based layered architecture and the off-line algorithms are used.

This paper presents the jointly use of constraint code (CC) and error correction codes (ECC) for the reliability enhancement in Multi-level cell NAND flash memories. In the proposed system, the constraint code helps transform the user data distribution, adapting to the asymmetry in error behavior of MLC NAND flash memories and the ECC corrects more errors thanks to the prior information from the data distribution. The compatibility of CC and ECC is analyzed, and the information loss is shown to be negligible, especially for the use in MLC NAND flash memories. Simulation under practical MLC NAND flash error model has shown that the proposed scheme can improve remarkably output error rate and reduce read latency in these memories.

The soft-decision Low-Density Parity-Check (LDPC) decoders have been applied in several storage systems thanks to their powerful error correction capability. However, these systems may suffer a long read latency since the soft-decision decoders require an intensive computations as well as a long sensing time for the soft-information before decoding. In this paper, we modify the recent-introduced Probabilistic Parallel Bit-Flipping (PPBF) LDPC decoder, to use on the storage systems in replacing the soft decision decoders, to improve the memory reading speed. The modified decoder is named Non-Syndrome Probabilistic Parallel Bit-Flipping (NS-PPBF). A special flipping mechanism is introduced such that the decoder can stop flipping without requiring the syndrome check results, which helps significantly improve the decoding frequency. We provide also the hardware architecture to implement NS-PPBF on the LDPC code used on the memory systems, which are usually very long block length with very high rate. The advantages of using NS-PPBF decoder in terms of error correction and decoding throughput are confirmed by the simulating decoding performance and the hardware synthesis.

This paper introduces a new approach to cost-effective, high-throughput hardware designs for low-density parity-check (LDPC) decoders. The proposed approach, called nonsurjective finite alphabet iterative decoders (NS-FAIDs), exploits the robustness of message-passing LDPC decoders to inaccuracies in the calculation of exchanged messages, and it is shown to provide a unified framework for several designs previously proposed in the literature. NS-FAIDs are optimized by density evolution for regular and irregular LDPC codes, and are shown to provide different tradeoffs between hardware complexity and decoding performance. Two hardware architectures targeting high-throughput applications are also proposed, integrating both Min-Sum (MS) and NS-FAID decoding kernels. ASIC post synthesis implementation results on 65-nm CMOS technology show that NS-FAIDs yield significant improvements in the throughput to area ratio, by up to 58.75% with respect to the MS decoder, with even better or only slightly degraded error correction performance.

The novelty of this paper is to propose a new LDPC decoder called Sign-Preserving Noise-Aided Min-Sum (SP-NA-MS) decoder that improves the decoding performance compared to classical Offset Min-Sum (OMS) decoder when messages are quantized, with only 3 or 4 bits. The particularity of the SP-NA-MS decoder is that the variable-to-check messages are never set to 0, and always carry the sign information. Moreover, the decoder incorporates random perturbation due to deliberate noise injection. The parameters of the SP-NA-MS decoders are optimized in the asymptotic limit of the code length thanks to the Density Evolution (DE) method. The finite-length simulations confirm the conclusions of the DE analysis and gain of up to 0.3 dB in SNR can be obtained compared to regular OMS with same quantization level.

This paper proposes a generalization of the recently introduced successive cancellation flip (SCFlip) decoding of polar codes, characterized by a number of extra decoding attempts, where one or several positions are flipped from the standard SC decoding. To make such an approach effective, we first introduce the concept of higher order bit flips and propose a new metric to determine the bit flips that are more likely to correct the trajectory of the SC decoding. We then propose a generalized SCFlip decoding algorithm, referred to as dynamic-SCFlip (D-SCFlip), which dynamically builds a list of candidate bit flips, while guaranteeing that the next attempt has the highest probability of success among the remaining ones. Simulation results show that D-SCFlip is an effective alternative to SC-list decoding of polar codes, by providing very good error correcting performance, with an average computation complexity close to the one of the SC decoder.

This paper presents an architecture-aware Progressive Edge Growth (PEG)-based construction method for Low-Density Parity-Check (LDPC) codes. We target optimization through code construction for layered architectures with pipelined processing and memory organized in single-port banks. For a given layered Quasy-Cyclic Low-Density Parity-Check (QC-LDPC) decoder architecture configuration, the code constraints need to maximize hardware usage efficiency. Implementation results for Field-Programmable Gate Array (FPGA) technology suggest that the codes obtained using the proposed algorithm have a throughput increase of 39% up to 110%, due to the increase in working frequency obtained by using pipeline.