Heterogeneous integration (HI) opens up a new dimension to improve system-level functionality, performance, power, form factor, and cost. Both 3DIC interconnect and monolithic CMOS technology affect the HI strategy and cost, as well as die-to-die data interface design. A novel 3D package, with a 2nm SOC die copper-bonded on an RDL interposer, is analyzed for power integrity and thermal, mechanical, and electrical properties to illustrate co-optimization by modeling.

We explore six different PR (Power Rail) design options in the range of library cell heights from 100 nm to 130 nm for the 1nm design rules (i.e. CPP (Contacted Poly Pitch) of 40 nm and minimum MP (Metal Pitch) of 20 nm). All these design options include 4 tracks for signal routing but different width of the power rails, ranging from conventional power rail design to the power rails having larger thickness than the signal wires on the same metal layer; BPR (Buried Power Rails); and a combination of the conventional and buried power rails. Ru (ruthenium) and Mo (molybdenum) metals with subtractive process (i.e. deposit and etch instead of the damascene process) are considered for both the power rail and the signal routing. The six technology/design options are benchmarked based on PPA (Power-Performance-Area) analysis of a routed GPU (Graphics Processing Unit) logic block operated at HP (High Performance).

Instead of marching from one crisply defined technology node to the next with an uncertain timeline, industry is transitioning toward annual technology updates driven by a schedule, but with an uncertain transistor density increase. Full node updates are expected every other year, with "half-node" updates in between. Pitch scaling began slowing after the 10nm node and is expected to practically cease by the 1nm node. Despite that, transistor density is expected to continue increasing at a similar pace of 45% density increase per node (or 20% per year) through the 1nm node, fueled by increasingly sophisticated Design-Technology Co-Optimization (DTCO) and Electronic Design Automation (EDA) advances.

We explore four different technology and design options for transistors and library cells for a low power supply voltage of 0.4 V and circuit statistics representative of artificial intelligence (AI) applications. The design rules correspond to 2nm node with cell heights of 100-110 nm and 30 nm gate pitch. Holistic analysis of the RO (Ring Oscillator) behavior, including MOL parasitics, all major variability sources, and stress proximity effects suggests that different FinFET and nanoslab transistor design options exhibit a wide range of power and performance differences. The key to improve FinFET PPA is to avoid fin cuts to maintain strong PMOS performance, and a key to improve SS corner delay is to use nanoslabs with tighter variability control.

Fast parallel algorithms are presented for updating minimum spanning trees, connected components and bridges of an undirected graph when a minor change is made to the graph such as addition or deletion of a vertex or an edge. The machine model used is a parallel random access machine that allows simultaneous reads as well as simultaneous writes into the same memory location. In the latter case one processor succeeds but we do not know which. The algorithms described in this paper require O(1) time and are efficient when compared to previously known O(logn) time algorithms for initial computation of the above mentioned graph properties on this model. An important feature of our algorithms is their versatility, that is, they can be adapted to run efficiently on all variations of this model with very little modification.

It is known that the layout area of a planar graph is influenced most by input parameters such as the size of its nodes, and its resemblance to an outerplanar graph. The latter is measured by the gauge of the graph. We examine the area-optimality of these layouts by exhibiting gauge and degree sensitive lower bounds on layout area. These results span the spectrum between outerplanar graphs, which have gauge 1, and arbitrary planar graphs, which may have gauge Ω(N), while simultaneously allowing vertices of arbitrarily large degree. In cases where we cannot establish optimality, our bounds place previous results in context by demonstrating gaps between the lower and upper bounds which are sensitive to these parameters. Moreover, we establish matching lower bounds in these cases for corresponding nonplanar graphs having identical partitioning characteristics. Previous gauge and degree sensitive techniques for finding layouts of planar graphs did not consider minimizing the maximum wire length. We address this problem briefly to provide evidence that results similar to layout area can be obtained for this problem as well.

A general method to find area-efficient VLSI layouts of graphs of arbitrary degree is presented. For graphs of maximum degree Δ, the layouts obtained are smaller by a factor of Δ2 than those obtained using existing methods. Optimal planar layouts, and near-optimal nonplanar layouts are also derived for planar graphs of arbitrary degree and gauge. The results span the spectrum between outerplanar graphs (gauge 1), and arbitrary planar graphs (gauge O(n)). Optimality is established by developing families of planar graphs of varying gauge and degree, and proving lower bounds on their layout area. These techniques can be combined to exhibit a trade-off between area and the number of contact cuts. The resulting scheme is sensitive to all three parameters that affect the area: the maximum degree, the gauge, and the number of contact cuts.

Structured ASICs are an emerging new class of ASICs that attempt to bridge the widening gap in per-unit manufacturing costs, non recurring engineering (NRE) costs, power consumption, and performance between zero-mask programmable devices such as FPGAs and devices such as cell based ASICs, which require new custom designed masks for every ASIC. They offer an intermediate trade-off point between the two extremes of the very high per unit cost, but zero non-recurring cost of FPGAs, and the very low per unit cost, but very high non-recurring cost of cell based ASICs. They also offer a similar, intermediate trade-off point between the two extremes for performance and power consumption. A common theme across all structured ASICs is the use of a circuit fabric that has a regular, repeating pattern of elementary building blocks that can be programmed using one or more masks to implement an ASIC device. In this paper, we describe the considerations involved in designing the regular circuit fabrics underlying structured ASIC offerings.