This paper outlines the Nallatech Accelerator Layer (NAL) and its relationship to Intel’s Accelerator Abstraction Layer. The NAL is looked at in its academicion Layer. The NAL is looked at in its academic context. Hardware platforms that support the NAL are discussed: the Nallatech H101, the Intel FSB-FPGA Module and the BenOne PCIe. The Intel QuickAssist Technology initiative and its associated Accelerator Abstraction Layer (AAL) are introduced.ion Layer (AAL) are introduced. To demonstrate the NAL system, two closed-form expressions are implemented. These functions are singleprecision floating-point, and make use of arithmetic operations and elementary functions. The functions selected were the probability density function (PDF) and the Black-Scholes-Merton options pricing formula (BSM). These functions were implemented on a dual-core Opteron, a Nallatech H101 card using the NAL, a Nallatech BenOne PCIe card, an NVIDIA G80 using CUDA and a Cell BE system. The GPU system showed the best silicon performance for the implementation of these kernels. Including data transfer times, the BenOne PCIe had the highest performance.

FPGAs have established performance advantages over other processing technologies. Difficulties in achieving high design productivity counterbalance these performance advantages. High-level languages (HLLs) targeting FPGAs together with low-level core libraries have the potential to overcome these productivity challenges. It is desirable to possess an industry standard for the integration of core libraries into FPGA HLLs. The OpenFPGA CORELIB group is working towards this end. The authors present an implementation of a core library: A library of floating-point elementary transcendental functions targeted at DIME-C, an FPGA HLL, and Xilinx Virtex-4 FPGAs. The paper contrasts three methods of creating pipelined mathematical cores: Using DIME-C creation, using VHDL and using System Generator. Implementation results, comparisons with software and general conclusions about elementary functions on FPGAs are given.

Research into the use of FPGAs in Image Processing began in earnest at the beginning of the 1990s. Since then, many thousands of publications have pointed to the computational capabilities of FPGAs. During this time, FPGAs have seen the application space to which they are applicable grow in tandem with their logic densities. When investigating a particular application, researchers compare FPGAs with alternative technologies such as Digital Signal Processors (DSPs), Application-Specific Integrated Cir-cuits (ASICs), microprocessors and vector processors. The metrics for comparison depend on the needs of the application, and include such measurements as: raw performance, power consumption, unit cost, board footprint, non-recurring engineering cost, design time and design cost. The key metrics for a par-ticular application may also include ratios of these metrics, e.g. power/performance, or performance/unit cost. The work detailed in this paper compares a 90nm-process commodity microprocessor with a plat-form based around a 90nm-process FPGA, focussing on design time and raw performance. The application chosen for implementation was a minimum entropy restoration of star-field images (see [1] for an introduction), with simulated annealing used to converge towards the globally-optimum solution. This application was not chosen in the belief that it would particularly suit one technology over another, but was instead selected as being representative of a computationally intense image-processing application.

One of the greatest perceived barriers to the widespread use of FPGAs in image processing is the difficulty for application specialists of developing algorithms on reconfigurable hardware. Minimum entropy deconvolution (MED) techniques have been shown to be effective in the restoration of star-field images. This paper reports on an attempt to implement a MED algorithm using simulated annealing, first on a microprocessor, then on an FPGA. The FPGA implementation uses DIME-C, a C-to-gates compiler, coupled with a low-level core library to simplify the design task. Analysis of the C code and output from the DIME-C compiler guided the code optimisation. The paper reports on the design effort that this entailed and the resultant performance improvements.

Until relatively recently, users of FPGA-based computers have needed electronic-design skills to implement high-performance computing (HPC) algorithms. With the advent of high-level languages for FPGAs it is possible for non-experts in FPGA design to implement algorithms by describing them in a high-level syntax. A natural progression from developing high-level languages is to develop low-level libraries that support them.DIME-C is a high-level language that takes a subset of ANSI C as its input and outputs auto-generated hardware description language (HDL) and pre-synthesised netlists. Within DIME-C, the authors have implemented a math library composed of single-precision, floating-point, elementary functions such as the natural exponential and logarithm. Complex, fully-pipelined algorithms can be described in ANSI-compatible C and implemented on FPGAs, delivering orders of magnitude speed-up over microprocessor implementations. Work is ongoing, expanding the library.The poster will detail project motivations and direction, speedup and resource-use measurements, C-code examples and multi-fpga examples.

FPGA-based reconfigurable computers can offer 10-1000 times speedup in many application domains over traditional microprocessor-based stored-program architectures. As a discipline, reconfigurable computing is in a period of change with little standards in place. It is becoming desirable to educate students in the principles of reconfigurable computing. This paper proposes that the abstraction benefits of high-level languages and floating-point arithmetic would shield students from the complexities of FPGA design and allow a syllabus with a greater focus on system-level aspects.

In this paper we present a field programmable gate array (FPGA) implementation of the Camellia encryption algorithm. Our implementation deeply sub-pipelines the algorithm for the FPGA architecture. Camellia has been included in both portfolios of the New European Schemes for Signatures, Integrity, and Encryption (NESSIE) for Europe and the Cryptography Research and Evaluation Committee (CRYPTREC) in Japan. The implementation is the fastest published throughput for the entire block ciphers recommended in both portfolios for NESSIE and CRYPTREC, and runs at a throughput of 33.25Gbit/sec.

We discuss the use of System Generator to hardware co-simulate in the FPGA versions of the AES-128 encryption algorithm. We show that the FPGA co-simulation of the AES can be achieved over 3 different bus types (TCP/IP, board-level TCP/IP, and PCI). One of the FPGA co-simulations is over 3 times faster running over a TCP/IP network distance off approximately 600 kilometres, than running a normal Simulink simulation on the host PC. Another hardware co-simulation time increases in the region of 4000% running over the PCI bus attached to the host PC. By having this FPGA co-simulation option, some of the IP cores in an FPGA system can be co-simulated, there by freeing up processing power on the host-PC for further developments in a system.

In this paper we discuss several key agile Camellia implementations. The New European Schemes for Signatures, Integrity, and Encryption (NESSIE) selected Camellia in its portfolio of strong cryptographic algorithms for protecting the information society. In order for an encryption core to be key agile it must be able to accept new secret keys as well as data on every clock cycle. We discuss the design and implementation of the Camellia algorithm for a FPGA. We obtain a throughput of 17.4 Gbit/sec when running on a Virtex-II XC2V4000 FPGA device.

We present various iterative Camellia encryption algorithm implementations. The algorithm uses a 128-bit key, which keeps the algorithm as small as possible. The purpose for this implementation is for low-cost or area-restricted implementations suitable for embedded or mobile applications. We discuss the design and implementation considerations for a feedback architecture and achieve a throughput of 426Mbits/sec without key scheduling and 388Mbit/sec with key scheduling.

FPGA co-simulation of an IP core is an important design flow step in IP and system development. In this paper, we discuss how, with Xilinx's system generator for DSP 3.1 (XSG), it is possible for multiple-users to hardware co-simulate IP cores over any distance via TCP/IP, sharing only one FPGA board resource. The hardware co-simulation strategy is mutually exclusive in that only one user at any one time can hardware co-simulate on the FPGA board. We demonstrate this with the use of two encryption cores, Camellia and AES-128 (advanced encryption standard), which have both been generated using the block-based tool. The sharing of the FPGA board is handled with a set of Matlab function commands.

We present a gigabit Ethernet AES (Advanced Encryption Standard) encryption engine. One of the main push factors in software-defined radio (SDR) is the use of programmable devices such as field programmable gate arrays (FPGAs) or digital signal processors (DSPs). Including such devices in SDR base station systems allows for reconfiguration and upgrade of the communication system and the application processing. Due to the increased concerns regarding secure information, we have implemented an AES encryption engine for data processing in an SDR system using one of the latest FPGAs available. The engine is capable of simultaneously processing 2 input and 2 output data streams of 1 gigabit each. As the system has been developed on an industrial scalable architecture, a further 3 FPGA daughter cards can be added to the board for further application processing, and each board could be one of many.

With the drive for software defined radio systems, FPGAs are playing a key role in handling the higher data rates to and from the analog front end of these systems. Furthermore, basestations are handling ever increasing channel numbers and the algorithm complexity is also continuing to increase. Traditionally systems scalability was achieved using farms of processors, associated with these, operating systems would provide the communication framework for managing system communication. The advent of FPGAs offers the capability to have a more flexible and powerful software defined radio. However the system architecture has fundamentally changed when FPGAs are used. When scaling a system based on FPGAs, operating systems running on processors become inappropriate and new mechanisms and tools are required to maximise the capability of the FPGA while enabling the systems engineer to have the communications tools to create the appropriate systems architecture. This presentation will look at how scalable FPGA systems can be created and link this to how it is used within software defined radio systems, this will look at multi-channel systems ranging from multiple single antenna channels to multi-antenna array applications such as smart antenna arrays.

In this paper, we discuss the use of System Generator to design a reconfigurable video encryption system. It includes the design of the AES (Advanced Encryption System) and Enigma encryption cores. As a result of using this design flow, we are able to efficiently implement our system and algorithms with a significant improvement on traditional design times, without compromise for performance.