A CMOS 100-140-GHz end-to-end receiver (RX) is presented that integrates the antenna input all the way to the bitstream output, while demodulating 64QAM/16QAM/QPSK entirely in the analog domain. A sequential asynchronous demodulation method enables 120-Gbps operation at a notably small baseband power consumption. Fabricated in a 22-nm FDSOI CMOS process, the RX achieves a peak conversion gain of 32 dB and a minimum noise figure (NF) of 9.5 dB. A wireless link measurement over a 15-cm distance demonstrates real-time demodulation of QPSK, 16QAM, and 64QAM at error vector magnitudes (EVMs) of-12, -17.5, and-17.2 dB, respectively. The RX prototype occupies a die area of 2.5 x 3 mm(2), including pad ring and test structures, and consumes 230 mW of power. This work underscores the feasibility of implementing low-power, sub-THz, high-speed RXs in nanoscale CMOS.

Purpose Brain–computer interfaces (BCIs) offer a pathway to restore ambulation in indi-viduals with spinal cord injury (SCI). However, existing BCI systems for gait are unidirectional and lack sensory feedback. This study aimed to demonstrate that a bidirectional brain–computer interface (BDBCI) can simultaneously enable real-time brain-controlled walking and artificial leg sensation via electrical stimulation of the sensory cortex. Methods Epilepsy patients undergoing bilateral interhemispheric subdural electrocorticog-raphy (ECoG) implantation were recruited for this proof-of-concept study. Motor mapping identified electrodes in the leg motor cortex for decoding stepping intent, while sensory stimu-lation mapping determined stimulation sites in the somatosensory cortex to elicit artificial leg percepts. A custom embedded BDBCI decoded motor intent in real time to actuate a robotic gait exoskeleton (RGE) from ECoG signals and delivered leg swing sensory feedback via direct cortical stimulation. Performance was assessed through correlations between cued and decoded states, sensory reliability tasks, and control experiments. Results One subject was recruited and achieved a high decoding performance (ρ = 0.92 ± 0.04, lag of 3.5 ± 0.5 s) across 10 runs of operating the BDBCI-controlled RGE. Bilateral leg percepts were validated through a blind step-counting task (92.8% accuracy, p < 10−6). Control experiments verified that decoding was not affected by stimulation artifacts. No adverse events were reported. Discussion This study establishes the feasibility of an embedded system BDBCI for restor-ing both motor control and artificial sensation of walking. Leveraging interhemispheric leg sen-sorimotor cortices is safe and yields superior decoding compared to prior lateral brain convexity approaches. These findings provide a foundation for translating BDBCI technology into fully implantable systems for SCI patients with paraplegia.

The design and implementation of a fully integrated CMOS antenna-to-bits 100 - 140 GHz receiver (RX) realizing 64QAM demodulation in analog-domain is presented. A sequential asynchronous QAM demodulation method is proposed that allows symbol detection, recovery, and extraction at 120-Gbps data rate at remarkably low power consumption. Fabricated in a 22-nm FDSOI CMOS process, this 100-140-GHz CMOS RX exhibits a measured maximum conversion gain of 32 dB and a minimum noise figure (NF) of 9.5 dB. A data rate of 120 Gbps is wirelessly measured at 15-cm distance with the received 64QAM signal being directly demodulated on-chip at a bit-error rate (BER) of 10−2. The measured RX sensitivity at this BER is -32 dBm. The prototype occupies 2.5 × 3mm2 of die area, including PADs and test circuits and consumes a total dc power of 230 m W.

Bi-directional brain computer interfaces (BD-BCIs) may restore brain-controlled walking and artificial leg sensation after spinal cord injury. Current BD-BCIs provide only simplistic "tingling" feedback, which lacks proprioceptive information to perceive critical gait events (leg swing, double support). This information must also be perceived adequately fast to facilitate timely motor responses. Here, we investigated utilizing primary sensory cortex (S1) direct cortical electrical stimulation (DCES) to deliver leg proprioceptive information and measured response times to artificial leg sensations. Subjects with subdural electrocorticogram electrodes over S1 leg areas participated in two tasks: (1) Proprioceptive acuity: subjects identified the difference between DCES-induced percepts emulating various leg swing speeds; (2) Sensory response: measuring subjects' reaction time to DCES-induced leg sensations, with DCES-hand, visual and auditory control conditions. Three subjects were recruited. Only one completed the proprioceptive assessment, achieving 80 fast/medium, medium/slow, and same speeds, respectively (p-value=1.9x10^-5). Response times for leg/hand percepts were 1007±413/599±171 ms, visual leg/hand responses were 528±137/384±84 ms, and auditory leg/hand responses were 393±106/352±93 ms, respectively. These results suggest proprioceptive information can be delivered artificially, but perception may be significantly delayed. Future work should address improving acuity, reducing response times, and expanding sensory modalities.

This paper presents a comprehensive analysis of the impact of a generic power amplifier’s (PA’s) output power on the bit-error-rate (BER) in a transceiver employing a 4Mquadrature amplitude modulation (QAM) scheme. The study highlights the dual effects of excessive and insufficient output power on system performance. On one hand, low output power reduces the signal-to-noise ratio (SNR) at the receiver, leading to increased BER. On the other hand, high output power pushes the PA into its nonlinear region, similarly degrading BER. A quantitative analysis is conducted to examine the combined influence of noise and nonlinearity on BER. From this analysis, the globally optimal PA output power that minimizes BER for a wireless system is derived. Theoretical insights are validated through system-level simulations, demonstrating the effectiveness and high accuracy of analytical expressions.

This invited paper presents a novel low-power wideband digital beamforming transceiver (TRX) array for integrated sensing and communications (ISAC). To achieve the much-needed full-duplex sensing and communication with high spectral and temporal efficiency, each array element employs a wideband, highly-linear, and blocker-tolerant transceiver architecture covering 20 - 50 GHz of bandwidth. On the receiver (RX) side, the N-path multi-phase mixers will still be employed as part of the RX to achieve tunable RF selectivity over a wide range of frequencies, excellent blocker/jammer tolerance, and great linearity. On the transmitter (TX) side, a three-phase current-mode direct conversion architecture is used to improve the output power and linearity, while rejecting the LO feedthrough. The LO generation and distribution network incorporates an all-digital phase-locked-based synthesizer followed by a frequency multiplier (M = 9) to allow a wider tuning range and a lower phase noise than a fundamental frequency synthesizer at mm-wave. The special attributes of this TRX architecture, including high linearity, low power, wide frequency range of coverage with high-Q RF selectivity, make it a strong hardware candidate for next-generation wideband ISAC links.

This article presents a bits-to-antenna wireless transmitter (TX), fully integrated in 45-nm CMOS SOI, capable of surpassing 100-Gb/s data rates. The unique method of directly forming the 64QAM constellation within the RF domain, using three QPSK sub-TXs with controlled amplitude weighting, effectively mitigates the complications introduced by power amplifier (PA) nonlinearity in high-order modulations. This strategic approach opens avenues for significant enhancements in bandwidth and output power. This article further explores additional advantages of this TX design, such as local oscillator (LO) leakage suppression and improved output power, while going through the specifics of circuit block implementations. With a 40-GHz RF bandwidth, the RF-64QAM TX prototype achieves a measured data rate of 120 Gb/s with an effective isotropic radiated power (EIRP) of 16 dBm.

A 49-63 GHz phase-locked stepped chirp frequency modulated continuous wave (FMCW) radar transceiver (TRX) in a 22-nm fully depleted silicon on insulator (FD-SOI) process is presented. To achieve the desired large bandwidth (BW), the frequency range is split into two sub-chirps, each controlled by distinct phase-locked loops (PLLs)-a reference PLL and a mixing PLL. This novel dual-PLL architecture facilitates a wide effective BW without the need for designing ultra-wideband TRX blocks. This radar TRX supports both free-running and phase-locked operations. The CMOS chip is co-integrated with linear arrays of series-fed patch antennas for each frequency band. The measured effective isotropic radiated power (EIRP) is 9 dBm with a phase noise (PN) of -101.09 dBc/Hz at 1 MHz offset at 56 GHz. The receiver (RX) achieves a 10-dB noise figure (NF). The radar field measurement demonstrates a maximum distance of 5 m and a range resolution of 1.4 cm.

Current treatments for paraplegia induced by spinal cord injury (SCI) are often limited by the severity of the injury. The accompanying loss of sensory and motor functions often results in reliance on wheelchairs, which in turn causes reduced quality of life and increased risk of co-morbidities. While brain-computer interfaces (BCIs) for ambulation have shown promise in restoring or replacing lower extremity motor functions, none so far have simultaneously implemented sensory feedback functions. Additionally, many existing BCIs for ambulation rely on bulky external hardware that make them ill-suited for non-research set-tings. Here, we present an embedded bi-directional BCI (BDBCI), that restores motor function by enabling neural control over a robotic gait exoskeleton (RGE) and delivers sensory feedback via direct cortical electrical stimulation (DCES) in response to RGE leg swing. A first demonstration with this system was performed with a single subject implanted with electrocorticography electrodes, achieving an average lag-optimized cross-correlation of 0.80±0.08 between cues and decoded states over 5 runs.

This paper presents a single-chip bits-to-antenna transmitter (TX) for >100Gbps in 45nm CMOS SOI. The construction of the 64QAM constellation is achieved directly in the RF domain by utilizing three QPSK sub-TXs with weighted amplitude. This method significantly reduces the need to address power amplifier nonlinear effects in high-order modulation, thereby creating room for TX enhancements in both bandwidth and output power. To further improve TX performance, multi-step phase alignment strategies, and a local oscillator leakage suppression technique have been incorporated. With 40-GHz RF bandwidth, the RF-64QAM TX prototype is able to achieve a measured data rate of 120Gbps with 15dBm effective isotropic radiated power (EIRP).

This study aims to estimate the maximum power consumption that guarantees a thermally safe operation for a titanium-enclosed chest wall unit (CWU) subcutaneously implanted in the pre-pectoral area. This unit is a central piece of an envisioned fully-implantable bi-directional brain–computer interface (BD-BCI). To this end, we created a thermal simulation model using the finite element method implemented in COMSOL. We also performed a sensitivity analysis to ensure that our predictions were robust against the natural variation of physiological and environmental parameters. Based on this analysis, we predict that the CWU can consume between 378 and 538 mW of power without raising the surrounding tissue’s temperature above the thermal safety threshold of 2 ^∘ C. This power budget should be sufficient to power all of the CWU’s basic functionalities, which include training the decoder, online decoding, wireless data transmission, and cortical stimulation. This power budget assessment provides an important specification for the design of a CWU—an integral part of a fully-implantable BD-BCI system.

A CMOS low-power, wideband, transformer-less, low noise amplifier (LNA), operating in the F-Band (90 - 130 GHz), tailored for 6G receivers is introduced. This work marks the first utilization of a complementary NMOS-PMOS inverter topology at above 100 GHz frequencies, showcasing not only low noise-efficiency factor (NEF) and high g(m)/I efficiency but also unparalleled energy efficiency due to the inherent current re-using feature of this structure. The stagger tuning across five gain stages facilitates a wide 40 GHz of RF bandwidth around the carrier frequency of 110 GHz. The use of simple CPW-based-matching networks rather than transformers leads to more precise electromagnetic modeling of the constituent passives. The proposed LNA is integrated with a previously-characterized down-conversion circuit to simplify the measurement process. The design, fabricated in a 22-nm FD-SOI CMOS process, occupies 0.08 mm(2) of silicon area and exhibits a minimum noise figure of 6.5 dB, while consuming only 7.5 mW of DC power. This power efficiency coupled with a low noise figure represents a new benchmark in CMOS LNAs at this frequency range.

This brief presents a novel isolated frequency compensation (IFC) technique for ultra-low-power (ULP) low-noise two-stage operational transconductance amplifiers (OTAs) with high gain-bandwidth (GBW) products. The IFC technique stabilizes the OTA in two steps. First, it pushes the first non-dominant pole of the OTA to higher frequencies using an isolated Miller capacitor. Second, it employs a local feed-forward path to create a zero and nullify the first non-dominant pole through pole zero cancellation. This allows the compensated OTA to reach higher GBW for a given bias current compared to conventional frequency-compensation methods. Fabricated in a standard 180-nm CMOS technology, the proposed circuit operates in sub-threshold and achieves 3 MHz of GBW and 2.3 V/mu s of average slew rate for a 45 pF capacitive load, while consuming a total current of 1.8 mu A from a 1.8-V supply. In addition, the proposed circuit achieves a measured common-mode rejection ratio (CMRR) of >= 70 dB for a bandwidth of up to 100 kHz.

This work presents a bi-directional brain-computer interface (BD-BCI) including a high-dynamic-range (HDR) two-step time-domain neural acquisition (TTNA) system and a high-voltage (HV) multipolar neural stimulation system incorporating dual-mode time-based charge balancing (DTCB) technique. The proposed TTNA includes four independent recording modules that can sense microvolt neural signals while tolerating large stimulation artifacts. In addition, it exhibits an integrated input-referred noise of 2.3 μ Vrms from 0.1- to 250-Hz and can handle a linear input-signal swing of up to 340 mVPP. The multipolar stimulator is composed of four standalone stimulators each with a maximum current of up to 14 mA (±20-V of voltage compliance) and 8-bit resolution. An inter-channel interference cancellation circuitry is introduced to preserve the accuracy and effectiveness of the DTCB method in the multipolar-stimulation configuration. Fabricated in an HV 180-nm CMOS technology, the BD-BCI chipset undergoes extensive in-vitro and in-vivo evaluations. The recording system achieves a measured SNDR, SFDR, and CMRR of 84.8 dB, 89.6 dB, and >105 dB, respectively. The measurement results verify that the stimulation system is capable of performing high-precision charge balancing with ±2 mV and ±7.5 mV accuracy in the interpulse-bounded time-based charge balancing (TCB) and artifactless TCB modes, respectively.

Objective. Invasive brain-computer interfaces (BCIs) have shown promise in restoring motor function to those paralyzed by neurological injuries. These systems also have the ability to restore sensation via cortical electrostimulation. Cortical stimulation produces strong artifacts that can obscure neural signals or saturate recording amplifiers. While front-end hardware techniques can alleviate this problem, residual artifacts generally persist and must be suppressed by back-end methods. Approach. We have developed a technique based on pre-whitening and null projection (PWNP) and tested its ability to suppress stimulation artifacts in electroencephalogram (EEG), electrocorticogram (ECoG) and microelectrode array (MEA) signals from five human subjects. Main results. In EEG signals contaminated by narrow-band stimulation artifacts, the PWNP method achieved average artifact suppression between 32 and 34 dB, as measured by an increase in signal-to-interference ratio. In ECoG and MEA signals contaminated by broadband stimulation artifacts, our method suppressed artifacts by 78%-80% and 85%, respectively, as measured by a reduction in interference index. When compared to independent component analysis, which is considered the state-of-the-art technique for artifact suppression, our method achieved superior results, while being significantly easier to implement. Significance. PWNP can potentially act as an efficient method of artifact suppression to enable simultaneous stimulation and recording in bi-directional BCIs to biomimetically restore motor function.

The phrase distributed amplification (DA) was first introduced by Ginzton, Hewlett, Jasberg, and Noe in an article published in the August issue of the 1948 Proceedings of the IRE [1]. The authors presented "a new principle in wide-band amplifier design." They then went on to explain that "by an appropriate distribution of ordinary electron tubes along artificial transmission lines, it is possible to obtain amplification over much greater bandwidths than would be possible with ordinary circuits.

The aim of this study is to estimate the maximum power consumption that guarantees the thermal safety of a skull unit (SU). The SU is part of a fully-implantable bi-directional brain computer-interface (BD-BCI) system that aims to restore walking and leg sensation to those with spinal cord injury (SCI). To estimate the SU power budget, we created a bio-heat model using the finite element method (FEM) implemented in COMSOL. To ensure that our predictions were robust against the natural variation of the model’s parameters, we also performed a sensitivity analysis. Based on our simulations, we estimated that the SU can nominally consume up to 70 mW of power without raising the surrounding tissues’ temperature above the thermal safety threshold of 1°C. When considering the natural variation of the model’s parameters, we estimated that the power budget could range between 47 and 81 mW. This power budget should be sufficient to power the basic operations of the SU, including amplification, serialization and A/D conversion of the neural signals, as well as control of cortical stimulation. Determining the power budget is an important specification for the design of the SU and, in turn, the design of a fully-implantable BD-BCI system.

Electrocorticography (ECoG)-based bi-directional brain-computer interfaces (BD-BCls) have drawn increasing attention due to: (1) the need for concurrent stimulation and recording to restore human sensorimotor functions [1] and (2) decent spatial resolution and signal fidelity along with clinical practicality. On the stimulation side, such BD-BCls may require > 10mA of biphasic current to elicit artificial sensation and > 20V of voltage compliance to accommodate various bio-impedances [1]. The charge mismatch between the two stimulation phases leads to voltage build-up, causing electrode corrosion and tissue damage. Existing charge balancing (CB) techniques, e.g., charge-pack injection (CP1) [2] and time-based charge balancing (TCB) [1], create CB current in the interpulse time interval, leading to unwanted secondary sensations and excessive stimulation artifacts (SAs). For recording, low input-referred noise (1RN) is necessary to acquire small neural signals (NSs) while a large dynamic range (DR) is required to accommodate large SAs. Existing recording systems employ either SAR [1] or continuous-time deltasigma (CT-$\Delta\Sigma$) [3] ADCs (Fig. 4). The former has limited DR due to the DAC mismatch, and the latter suffers from distortion caused by the large-amplitude sharp SAs within the loop delay. Although in [4], the sampling frequency of the $\Delta\Sigma-$ADC is adaptively varied to accommodate SAs, the required settling time is large. To address the above issues, this work presents an ECoG-based BD-BCI that includes: (1) a high-voltage (HV) stimulation system with dual-mode time-based charge balancing (DTCB) and (2) a high-dynamic-range (HDR) time-domain pipelined neural acquisition (TPNA) system.

This paper provides an overview of broadband terahertz antenna elements and arrays for integrated communication systems. The fundamental challenges of integrated on-chip and off-chip antenna design, the trade-offs between performance metrics, and the impact of interface between the chip and off-chip antennas are studied in detail. The limitations and benefits of various interface technologies are discussed. The deployment of printed circuit boards (PCB) and flexible printed circuits (FPC) technologies for implementation of efficient broadband antennas is compared against on-chip counterparts. As a proof of concept, an off-chip antenna for the 91–134 GHz is presented.

Realization of high-order modulation schemes directly in the RF domain enables the generation of spectrally efficient $4^{M}$ quadrature-amplitude-modulated ( $4^{M}$ QAM) symbols using the vectorial summation of $M$ quadrature phase-shift keying (QPSK) signals whose amplitudes are progressively scaled by a constant factor of two. Called RF-QAM, this approach leads to numerous advantages including the elimination of power-hungry digital-to-analog converter (DAC) and the mitigation of stringent linearity requirement of the front-end power amplifier (PA). This paper presents a comprehensive comparative study of RF-QAM and conventional transmitters. The design issues associated with the front end and the mixed-signal blocks for both architectures are investigated, and the performance of these two designs is compared. Various circuit- and system-level simulations verify the superior performance of the RF-QAM transmitter compared to the conventional counterpart.