This paper presents an alternative approach to saturation control in an integrator, that occurs in Sigma-Delta modulators (ΣΔMs). This solution simplifies the design process with a 1.2- V power supply and consumes significantly less power than conventional saturation control methods. Additionally, this solution provides a good phase margin, that guarantees the stability, without requiring additional compensation techniques, and it has the added benefit of reducing the gain of the integrator as the system enters saturation, while also maintaining integrator inputs fixed at the proper common-mode voltage. This innovative approach offers a promising solution for efficient and stable saturation control in ΣΔM integrators, preventing distortion in the output signal, with potential applications in a wide range of electronic systems, such as audio systems. The circuit has been designed in a 90-nm CMOS technology.

This paper presents a Class-D audio amplifier, fully compatible with standard BCD technologies, that features in the direct signal path an ADC ( $\Sigma\Delta$ modulator), a digital third-order loop-filter and digital PWM. The overall closed-loop mixed-signal architecture pushes most of the signal processing towards the digital domain, thus allowing the use of scaled technologies to reduce cost and size. Moreover, the high gain developed by the digital filter and by the integrator inside the $\Sigma\Delta$ modulator, attenuates the residual high frequency ripple around the loop and concurrently improves the THD+N in the audio band. In this paper the feedback is closed after the output LC filter, thus mitigating the influence of its components on the amplifier transfer function and on the linearity. The proposed architecture achieves in simulation 120 dB of SNR and a THD of 0.01%-0.001 %, even in wide input signal conditions.

This paper presents an optimized current-steering digital to analog converter (DAC) designed for a Class-D audio amplifier. The DAC exploits the potential of a mixed-signal architecture, thus allowing to take advantage of the flexibility of the digital domain and the performance of analog solutions. The proposed converter exploits an optimized differential data weighted averaging (DDWA) and an adaptive circuit that mitigate the mismatch and the switching spikes contribution, respectively. Moreover, the switches behave as a cascode for the current generators, thus reducing cost and area and making easier the design. The presented converter achieves up to 0.0003% total harmonic distortion (THD), 120-dBA dynamic range (DR) with 1.2-V power supply and a clock frequency of 4.6-MHz, and $5.19 \mu \mathrm{V}$ of noise. The circuit has been designed in 90-nm CMOS process technology with a total estimated area of 0.072-mm 2 .

This brief presents a hybrid ADC, by combining an incremental converter with a delta-sigma modulator ( $\Delta \Sigma \text{M}$ ) to achieve a high-dynamic response, intended for audio applications. The circuit uses a ‘zero + first’-order incremental converter with a 4-b quantizer and a third-order $\Delta \Sigma \text{M}$ . Combining the two binary outputs generates a 576-kHz 6-bit binary flow for directly driving a class-D amplifier. A 4-bit flash used in the incremental running at 1/16 the clock frequency and a one-shift DEM technique compensate for the capacitive mismatch and cancel its effect for input signals lower than −35 dB $_{FS}$ . The proposed ADC, fabricated in a 0.18- $\mu \text{m}$ CMOS process, occupies an active area of 1.2 mm 2 and consumes 7.2 mW with a 1.8-V supply. The circuit achieves an SNR/SNDR/DR of 96.8/94.45/106 dB for a 21-kHz signal bandwidth.

This paper presents a single-inductor-multiple-output (SIMO) dc-dc converter suitable for supplying a car-radio. From a single input, an automotive battery-supply (V-bat), the SIMO converter generates three regulated output voltages: V-bat+6.5 V boost, 4.5 V buck, and 1.8 V floating around half V-bat. A novel, reconfigurable power-stage is conceived and switched appropriately to generate the unique floating output among others. Regulated floating dual-slope (RFDS) drivers are proposed to limit the di/dt through the switches and to reduce the switching-noise. A continuous-time (CT) error-processor is implemented to generate the control-phases. The circuit withstands the 4-40 V range of car-battery variations and regulates in the 4.5-27 V range while remaining in the idle-state outside. The SIMO converter is embedded in a car-radio IC and fabricated in a 110-nm BCD process. The switching frequency is 2.4 MHz. The SIMO converter offers a peak power-efficiency of 86% at 2.7 W of output power and occupies an active area of 2.5 mm(2). The operating temperature range is -40 degrees C to + 150 degrees C. In a 4-channel car-radio, the proposed SIMO converter reduces the quiescent power-dissipation by up to 36% while having negligible effect on the audio performance.

The design of Class-D audio power amplifiers [1] for car radio is challenging because of the large voltage variation of the automotive battery. During crank and dump, the 14.4V battery voltage may sharply (in less than 2ms) drop down to 4V or rise up to 40V. For a proper operation, the supply voltages of the Class-D amplifier must be properly controlled for all the battery conditions. The block diagram of the Class-D power amplifier in Fig. 27.3.1 helps in defining the set of required supply voltages. The power audio stage uses n (n =1,...,4) channels of high and low-side switches both made by n-type transistors. The choice optimizes the on-resistance and the gate capacitance to achieve the best efficiency, but requires a boosted voltage (V boost ) to drive the high-side devices. A regulated low voltage (V reg-low =4.5V) supplies the driver of N pow-LS . As the digital and analog processing are performed at V ba /2 to improve the system SNR, the digital core uses a floating voltage (V floatH -V floatL =1.8V) across V bat /2.

This paper presents two design considerations for integrated high-voltage DC-DC converters in automobile and industrial applications. The proposed solutions include (i) a quasi soft-start technique using over-current protection (OCP) circuits and limited duty cycle control and (ii) a technique to drive a floating load-side switch that suppresses the effect of bond-wire bouncing on its gate-source voltage. The first technique avoids the conventional, overhead start-up circuits and significantly reduces the converter startup time. The second technique gains importance primarily from device reliability viewpoint in high-voltage (HV) conditions. The effectiveness of the proposed techniques has been verified with simulations at the transistor level using a 110-nm BCD technology.

This paper presents a level-shifting technique for high-voltage power converter applications. The proposed circuit effectively combines capacitive and active coupling of the input low (high) side signal to the output high (low) side to reduce the propagation delay of the level-shifting operation. By using the resulting circuit, (i) the high-side PMOS switch is driven at high speed and (ii) a quasi-zero voltage switching (ZVS) of the low side NMOS switch is achieved. The circuit has been designed and simulated at the transistor level using a 0.18-μm BCD process. At the high-side, remarkable simulated average level-shifter propagation delay and total driving delay have been achieved: 0.5 ns and 1.9 ns, respectively. The proposed level-shifter consumes 48.5 μA of average current.

This paper presents a feedback strategy to make a two level, PWM modulated amplifier highly immune to the effects of the output LC filter and the frequency response independent on the loudspeaker characteristics. It exploits a multiloop structure and the demodulation filter is put into the feedback path. The proposed solution is first analyzed from a theoretical point of view; then the results are verified by measurements on an integrated amplifier.

High-efficiency speakers significantly improve electrical to sound power conversion efficiency by reducing the power dissipation over the speaker coil. However, they require some equalization of the input signal. In this paper, a new driving technique based on a pulsewidth-modulation switching amplifier is presented. This exploits a double voltage/current feedback to obtain automatic equalization. Furthermore, the double feedback allows the output resonant filter to be included in the feedback path, compensating for its nonlinearity. Finally, the mixed feedback acts as intrinsic current limiter. Both theoretical analysis and simulations demonstrate that this system is feasible. The results were also confirmed by measurements using a prototype