Segmented high-purity germanium detectors are at the heart of cutting-edge gamma spectroscopy. However, their technical and manufacturing specifications are not known, since they are provided by industry. To bridge this gap, Italy’s INFN launched the N3G Project, an initiative to design new segmented high-purity germanium detectors while acquiring the technical expertise to build, manage, and maintain them independently. In this framework, the current paper offers a novel contribution. The innovative system designed to electrically connect the electrodes of the detector to the front-end electronics will be described and its low impact on the detector leakage current will be shown. Moreover, the architecture of a new integrated charge sensitive pre-amplifier will be reported and its validation will be presented. The circuit demonstrated excellent linearity and low noise. An integral non-linearity factor of $\mathbf{0. 4} \%$ was found and an optimum equivalent noise charge of 108 root-meansquare electrons was measured for a 15 pF equivalent electrode capacitance.
In this paper, a comparative analysis is performed between two techniques previously presented in the literature for generating voltage references ($V_{R E F}$), focusing on their stability with respect to variations in temperature and process parameters, in the context of integrated micropower management circuits. The first technique combines Proportional-to-Absolute-Temperature (PTAT) and Complementary-to-AbsoluteTemperature (CTAT) currents generated with the support of operational amplifiers, to generate the ($V_{R E F}$). The second technique utilizes a self-biased current mirror for generating a PTAT current, while the CTAT current is again generated with the previously used opamp-based circuit, and both currents are added to generate the $V_{R E F}$. A band-gap reference (BGR) design involves a bandgap core, a summing circuit, and a start-up circuit to apply the correct bias. Both BGR1 and BGR2 circuitry provides a voltage reference of 900 mV over $-40^{\circ} \mathrm{C}$ to $100^{\circ} \mathrm{C}$ temperature range with a power supply (VDD) of 1.2 V.
The growing demand for reliable wearable devices that can continuously monitor vital signs and track health under various conditions, impose challenging constraints on battery life. Wearable devices typically include a photoplethysmogram (PPG) sensor, which is used for various applications such as monitoring heart rate (HR) and blood oxygenation (SpO2). The efficiency of these applications depends on the quality of the PPG sensor, which acquires raw data through the analog front-end and transmits it externally. This paper presents a novel Register Transfer Level (RTL) block that evaluates the quality of the PPG signal. This Signal Quality Assessment (SQA) RTL block is derived from postprocessing algorithms and converted into a real-time singlesample evaluation algorithm and provides significant benefits to the sensor with minimal overhead in terms of energy and area consumption.
An analog integrated decision tree classifier designed for real-time dementia prediction with low power consumption is presented in this work. The design uses sub-threshold analog circuitry, including a squarer circuit, analog multiplier, and current comparator, to achieve an exceptionally low power consumption of $729 n W$ and a classification speed of $570 K$ inferences per second. It is developed using the TSMC 65nm CMOS process. The classifier consistently performed well despite process, voltage, and temperature fluctuations, achieving an average accuracy of $90.63 \%$ when tested on a dataset representative of machine operating conditions. Through the prediction of dementia neurological disorder, this method offers effective, real-time, edge-based classification in biomedical settings.
A simple topology for a $\mathrm{g}_{\mathrm{m}}-\mathrm{C}$ complex filter to be used in a low-IF low power wireless receiver is proposed and analyzed. The result is a set of close-form equations that allows for a straightforward design procedure. The proposed analysis is validated by transistor-level simulations on a design example in a 22 nm CMOS technology.
This paper presents a low-noise amplifier and a power amplifier for W-band applications in a silicon-photonic 250 nm SiGe BiCMOS EPIC technology, with the aim of illustrating how bandwidth, noise figure and output power compare against circuits fabricated in simpler non-EPIC technologies. Furthermore, the designed circuits were also combined with a variable gain amplifier. The chips have been manufactured and characterized; the experimental results are here reported. A demonstration of these essential components for a photonic-aided wireless radio communication system in an silicon photonic technology have not yet been documented in the literature.
Time-interleaved ADCs are a key building block in mm-wave receivers, where the use of multi-GHz signal bandwidths requires high-performance wide-band data conversion. It is therefore necessary to explore the beamforming receiver system impact of different time-interleaved ADC parameters and limitations, such as number of interleaved channels, mismatches between channels, non-idealities of the subADCs, and correlation between sub-ADCs. This paper presents a scalable testbench in MATLAB/Simulink which models time-interleaved pipeline ADCs with high fidelity. The testbench is used to investigate the impact of time-interleaving errors on digital, hybrid, and analog beamforming receivers, both with and without interfering signals. Results show that the combination of time-interleaving errors and interference causes a degradation in beamforming performance, even at relatively low SNDR levels. The effect is more pronounced in digital beamforming compared to hybrid and analog beamforming.
This paper presents a comparative analysis of 1stage and 2 -stage $60-\mathrm{GHz}$ low-noise amplifiers (LNAs) in $28-\mathrm{nm}$ bulk CMOS technology. The focus is on key design parameters such as gain, noise figure (NF), 3-dB bandwidth ($B W_{3 \mathrm{~dB}}$), and linearity. The LNAs are optimized for millimeter-wave (mmwave) applications, exploiting a pseudo-differential topology with an integrated input balun for both electro-static discharge (ESD) protection and optimal input/noise matching, while maintaining low power consumption. The study reports a maximum voltage gain of 21.4 dB and 19.3 dB at 60 GHz with bandwidth of 2 GHz and 6 GHz for the 1 -stage/ 2 -stage LNAs, respectively. Moreover, the LNAs exhibit noise figure values of 6.3 dB and $6.9 \mathrm{~dB}, 1-\mathrm{dB}$ compression point ($I P_{1 \mathrm{~dB}}$) of -19.4 dBm and -14.4 dBm, and total power consumption of 5.2 mW and 8.3 mW for 1 -stage $/ 2$-stage configurations, respectively. These results demonstrate an effective trade-off between performance and power efficiency, highlighting pros and cons of 1-stage and 2-stage LNAs for mm-wave applications.
Multichannel data management poses considerable challenges; it is essential in a world increasingly driven by big data in both scientific research and industrial applications. Histogramming remains a key operation for analyzing signal distributions, noise profiles, and threshold behaviors in multichannel detector systems. This paper presents a fully hardwareembedded real-time histogramming module integrated into a multi-purpose digitalizer (MPD) platform based on an Xilinx Kintex-7 FPGA. The system captures 12-bit ADC data at $\mathbf{4 0}$ MHz across multiple channels and allows direct user access via a 1 Gbps TCP/IP Ethernet interface. Moreover, a dualport block RAM architecture supports concurrent read and write operations across separate acquisition and system clock domains. At the same time, a compact control finite state machine ensures seamless state transitions without introducing dead time. Unlike hybrid FPGA-CPU architectures, the proposed design is entirely spatial and self-contained, making it well-suited for highthroughput, low-latency data.
Neuromuscular disorders (NMDs), such as myopathies and neuropathies, affect the communication between nerves and muscles and often lead to serious functional impairments. This study investigates the impact of preprocessing methods and machine learning models on the automated classification of NMDs using electromyography (EMG) data. We compare Convolutional Neural Networks, Extreme Gradient Boosting, and Light Gradient Boosting Machine on two binary classification tasks: Healthy vs. Myopathy and Healthy vs. Neuropathy. The analysis is conducted on an open dataset of invasive needle EMG recordings, serving as a preliminary step toward the future use of non-invasive surface EMG in wearable diagnostic tools. The results highlight the importance of preprocessing and show promising performance across all models.
A two-stage GaN operational transconductance amplifier is proposed, which uses a dynamic voltage shifter based on the switched-capacitor technique to achieve robustness against process tolerances. The dynamic voltage shifter overcomes the traditional limitations of GaN transconductance amplifiers, which are due to the lack of complementary transistors and large parameter variations. Indeed, the use of nchannel transistors for the input pair, current mirrors, and second stage gain makes the performance of the traditional transconductance amplifiers greatly dependent on process tolerances. For circuit validation, a two-stage amplifier was designed using the traditional and proposed approach. For this comparison, the model parameters of a $0.5-\mu \mathrm{m} \mathrm{GaN}$ technology and a power supply of 6 V were adopted. Under worst-case process conditions, the proposed two-stage amplifier achieves a gain and a linear swing that are 64 dB and 1 V, while the traditional amplifier provides only 34 dB and a few tens of millivolts, respectively, considering a THD of $\mathbf{- 4 0 ~ d B}$.
This paper presents a methodology for the design of band-pass $\Sigma \Delta$ modulators. The proposed procedure does not force the modulator central frequency $f_{n}$ to one quarter of the sampling frequency $\mathbf{f}_{\mathrm{s}}$ (or to one of its odd multiples), nor imposes each resonator to have an order higher than 2, as a 2 -path and an N-path transformation would respectively do. Starting from the synthesis of the noise transfer function (NTF), which can be accomplished using some MATLAB functions, it is possible to derive the transfer functions of the resonators making up the modulator. To validate the proposed methodology, this paper also illustrates the design of a $4^{\text {th }}$ order band-pass $\Sigma \Delta$ modulator having a $400-\mathrm{kHz}$ central frequency, a sampling frequency of 6.4 MHz and OSR equal to 160, used to drive an ultrasonic transducer and achieving a dynamic range of 72.5 dB.
This paper presents a 7-bit digital-to-time converter (DTC) architecture based on emitter-coupled logic (ECL), designed for noise-critical and radiation-hardened applications where low-volume components are required and CMOS technologies may prove inadequate. The proposed DTC employs a variable-slope delay mechanism utilizing a digitally controlled capacitor array, achieving a resolution of 530 femtoseconds (fs) and a delay range of 67.3 picoseconds ($\mathbf{p s}$). To enable the generation of clean square-wave outputs, two recovery stage topologies are analyzed. A modified ECL recovery stage, incorporating cross-coupled negative capacitance, is proposed to address the trade-off between phase noise and integral nonlinearity (INL). Simulation results indicate that the modified design achieves a systematic peak INL of 20 fs, representing a significant improvement over CMOS counterparts. The phase noise floor reaches $-160.8 \mathrm{dBc} / \mathrm{Hz}$, with a $\mathbf{4 0 0 - H z}$ flicker noise corner frequency at a $200-\mathrm{MHz}$ input signal, offering competitive noise performance. These benefits are realized at the cost of an increased power consumption of 24 mW.
This paper presents the complete design and electrical simulations of a volatile memory cell in 28 nm CMOS bulk technology resistant to Single Event Upset at 20 $\mathrm{MeV} \cdot \mathrm{cm}^{2} / \mathrm{mg}$ of Linear Energy Transfer. The circuit topology of the cell is based on a classic six-transistor structure, in which the storage latches have a feedback impedance which allows to reduce the current contribution on the pull-down/pull-up network in case of upset events, avoiding unwanted setup of the stored bit. To demonstrate the robustness of the cell against upset events, the current pulse signal generated by the incident particles passing through the silicon substrate was modelled and generated by MATLAB equations and subsequently moved to SPICE environment simulator for performance verification. In the presence of an incident charge pulse of $\mathbf{1 5. 5 ~ f C}$ (whose duration is of the order of $\mathbf{4 0 0 ~ p s}$) the single event current pulse has a peak of $60 \mu \mathrm{~A}$ and generates a voltage variation of -250 mV with respect to the ‘ 1 ‘ logic value (0.9 V as nominal supply voltage for Standard Process MOS Transistors in 28 nm CMOS) with a recovery time below 1% of 0.9 V of only 600 ps. The simulations were carried out assuming to operate in a SRAM bank of 32 words of 32 bits, thus including the capacitive effects of the bit-line routing. The cell operates with $\mathbf{1 0 ~ n s}$ per operation (for the READ, WRITE and HOLD states, respectively) and has an energy/bit of $\mathbf{1 0 8} \mathbf{f J}, \mathbf{6 4} \mathbf{f J}$ and $\mathbf{1 2 6} \mathbf{f J}$, for the WRITE, HOLD and READ operations, respectively.
This paper presents a regulator-less stacked-power delivery using solar cells as the photovoltaic (PV) energy harvester. There are critical challenges for current delivery in integrated circuits on chips while operating at low voltages. To address this issue, voltage stacking is a suggested method to deliver power in “a series” instead of the traditional “parallel” approach. This paper utilizes voltage stacking as the power delivery approach and an energy harvester with maximum power point tracking (MPPT) as the supply source. The harvester uses a nanofarad bulk capacitor ($\mathrm{C}_{\text {bulk }}$) as a small storage element. The proposed method proves advantages compared to the traditional. It requires half the number of solar cells (i.e 3) while the traditional one requires 6 solar cells. The area of PV harvester in traditional and proposed is approximately $32,897 \mathrm{~mm}^{2}$ and $16449 \mathrm{~mm}^{2}$ respectively. This results in a $\mathbf{5 0 \%}$ smaller area along with a decrease in cost. The architecture also results in Cbulk size reduction from 2.7 nF in traditional to 1 nF in the proposed, resulting in improved area efficiency and faster charging to the target supply voltage. Moreover, the architecture reduces the current by almost 50% which mitigates the challenge of low current delivery and can lead to supply noise reduction and better power delivery efficiency.
This paper compares, as a function of the efficiency, the small-signal performances of two output stage topologies for the development of ultra-fast response time Low-Dropout regulators (LDOs), based on the Flipped-Voltage Follower (FVF) cell. Although one of the alternatives achieves an higher efficiency for a given bandwidth, it suffers from reduced phase margin. To solve this issue, a technique able to extend the output stage bandwidth with improved efficiency and phase margin is presented. The implementation of a schematic-level prototype LDO in a $28-\mathrm{nm}$ bulk CMOS technology, which exceeds state-of-the-art dynamic performances, confirms the effectiveness of the proposed solution.
This paper proposes an enhanced low power logic control block equipped with SPI interface intended for controlling arrays of switches. Validation of the proposed control block architecture was achieved through silicon measurements at chip level which contains the digital block with a matrix structure meant to be addressed and updated by the controller. This design was realized in 65 nm CMOS technology, targeting operating voltages ranging from 1.0 V up to 2.5 V, across a wide interval, $-40^{\circ} \mathrm{C}-125^{\circ} \mathrm{C}$. High speed operation could be achieved, having a frequency operation above 70 MHz, very fast propagation delays, and below 2 ns data setup values.
In this paper, a comparative study of two capacitive isolation information transmission systems is conducted. Previously two systems designed for an AC-switch driving were proposed. Thanks to capacitive isolation, the proposed systems are compatible not only with CMOS technology but also with strong magnetic field environment such as MRI equipment. Both systems share the same modulator but differ in demodulator: one uses an inverter-based envelope detector and the other uses a current-source-based envelope detector. The comparison is based on Monte-Carlo (MC) simulation in purpose to compare the robustness in terms of carrier frequency stability, power consumption and signal delay between the two systems. To enhance the circuit robustness against technological dispersions, improvement has also been brought to the initial systems. Both systems are designed in CMOS HV $0.35 \mu \mathrm{~m}$ technology under 3.3 V supplies and MC simulations are given.
The reliability assessment and failure analysis of Microelectromechanical System (MEMS) mirrors is a rather new research area, where especially the influence of environmental and mechanical loads on the performance needs to be evaluated. The aim of this work is to test the reliability of two-dimensional (2D) resonant MEMS mirrors, which are driven electrostatically, under applied stress in order to find out after which time and at which stress levels the function of the mirror is affected or a breakage occurs. With the help of the used test setup several mirrors could be tested simultaneously and different mirror parameters could be logged. Measurements have been executed with a duration of approximately one month, where the mirrors were stressed by increasing the oscillation angle over time. The results showed that there are mirror parameters, which may indicate a failure of the mirror before it occurs. Especially a negative drift of the mirror frequency was observed before breakage. Additionally the results showed a correlation between temperature and mirror frequency and information about the distribution of the stress levels at which the mirrors break was gathered.
