The task of the final finish on the printed circuit board is to protect the copper surface and at the same time keep it active for the subsequent assembly steps. In high frequency applications, additionally the impact on the signal loss becomes of interest. Typically, the choice of the final finish is defined by the target application. The demands on solderability and bondability need to be considered and the acceptable price level needs to be defined. For the use in high frequency applications the signal integrity becomes of interest and adds on the reliability criteria such as solder joint reliability or corrosion resistance. In this study various surface finishes were tested towards their performance on insertion loss at high frequency. In contrast to earlier studies the frequency range was investigated up to 150 GHz and the impact of thermal or humid aging of the final finish was evaluated. Overall, seven different finishes have been selected including EPAG (Electroless palladium/Autocatalytic gold), I-Sn (Immersion tin), I-Ag (immersion silver), DIG (direct immersion gold), Au/Pd/Au (Gold/Palladium/Gold), ENIG (Electroless Nickel/Immersion Gold) with high and medium phosphorous Nickel and ENEPIG (Electroless Nickel/Electroless Palladium/Immersion Gold). The paper compiles the data for insertion loss versus frequency for the different final finishes at layer thicknesses as commonly used in the PCB industry. The results in the insertion loss performance are correlated to other properties of the different final finishes such as reliability and assembly performance to identify the best candidates for high frequency applications.

In this paper, we present numerical uncertainty quantification using polynomial chaos expansion and variance-based global sensitivity analysis of a microstrip fabricated on IC-substrates. Microstrip design parameters such as line width, trace height, substrate thickness, relative dielectric constant, and loss tangent are assumed to have Gaussian probability distribution depending on IC-substrate manufacturing processes. Those input parameter variations are represented by orthogonal polynomials and their coefficients. The impact of the varied design input parameters on the electrical characteristics such as a characteristic impedance and propagation constant is quantitatively analyzed. For computational efficiency, non-intrusive spectral projection method with Smolyak sparse grid technique is employed to mitigate the numerical multi-dimensional integration. Variance-based sensitivity analysis using Sobol indices is also performed for the investigation of significant input parameters on each output parameter at several frequencies.

This paper investigates the bandwidth extension achieved for a Doherty power amplifier topology, by using a packaging approach which minimizes packaging-related parasitic effects, such as the effective inductance of bonding wires. A Doherty power amplifier module is designed using a novel packaging approach by embedding the higher power RF transistors inside the module laminate. This embedded approach is compared against a more conventional previously developed demonstrator, which uses wire-bonded transistor dies. Initial simulations show that the embedded Doherty amplifier can extend the bandwidth from the initial 500 MHz to 800 MHz, while maintaining similar levels of output power, drain efficiency and transducer gain. Finally, the measured performance of the embedded and wire-bonded demonstrators is also analyzed and compared.

To accommodate the ever-growing data requirements in densely populated areas and address the need for high-resolution sensing in diverse next-generation applications, there is a noticeable trend towards utilizing large unallocated frequency bands above 100 GHz. To overcome the harsh propagation conditions, large-scale antenna arrays are crucial and urge the need for cost-effective, mass-manufacturable technologies. A dedicated Any-Layer High Density Interconnect PCB technology for highly efficient wireless D-band (110-170 GHz) systems is proposed. Specifically, the adapted stack accommodates broadband air-filled substrate-integrated-waveguide components for efficient long-range signal distribution and low-loss passives. The viability of the suggested technology platform is demonstrated by designing, fabricating and measuring several essential low-loss air-filled substrate-integrated-waveguide components, such as a dual rectangular filter, with a minimal insertion loss of 0.87 dB and 10 dB-matching within the (132.8-139.2 GHz) frequency band, and an air-filled waveguide with a routing loss of only 0.08 dB/mm and a flat amplitude variation within 0.01 dB/mm over the (115-155 GHz) frequency range. A broadband transition towards stripline, with a limited loss of 1.1 dB, is described to interface these waveguides with compactly integrated chips. A tolerance analysis is included as well as a comparison to the state of the art.

This paper presents an experimental characterization of grounded coplanar waveguides (GCPWs) with uncertainty analysis. GCPW lines to be analyzed were fabricated using different subtractive printed circuit board (PCB) manufacturing processes: panel plating method and pattern plating method. Using a modified multiline method, we have extracted the propagation constants with uncertainty propagation analysis. This considered instrumentation noise, length uncertainty, and impedance mismatch caused by variations in cross-section due to the fabrication capabilities of each manufacturing process. By reformulating the propagation constant, we obtained the attenuation per unit length and the effective relative permittivity as a function of frequencies up to 43.5 GHz with 95% confidence interval. These results showed good agreement with full-wave simulations and highlighted the differences between the PCB manufacturing processes.

Only a limited amount of research has been performed on the implementation of air-filled substrate-integrated-waveguide (AFSIW) systems in multi-layer PCB stacks at subterahertz frequencies. In this paper, we investigate the manufacturing reliability and the measurement repeatability based on several measurements of AFSIW transmission lines and three different filters on three separate PCB panels at D-band frequencies (110 GHz-170 GHz). A promising dual-cavity AFSIW filter with a steep roll-off on both sides of the passband is designed, fabricated and measured. The measured insertion loss is around 3 dB, while the out-of-band suppression is better than 30 dB.

The steadily increasing demand for higher data transmission rates leads to higher frequencies with greater bandwidth and at the same time reduced losses. The size of air-filled waveguides are frequency dependent, therefore an integration into a PCB is possible above 100 GHz in the D and G band region making them an interesting technology for 6G communication and radar application. Usually, substrate integrated waveguides (SIW) are manufactured in mass production with sidewalls made of Copper filled laser micro via fences. However, with these copper laser micro via fences used as sidewalls, losses can become excessive due to parallel plate mode excitation. Additionally, roughness of waveguide top and bottom walls must be minimized to reduce conductor losses. In order to meet the increased requirements of ultra-low loss, broadband signal transfer at D band we present an air-filled substrate integrated waveguide (AFSIW) technology with solid sidewalls and smooth top and bottom walls, which is suitable for mass production. In this paper, the AFSIW technology is proposed for ultra-low loss connections 140 GHz radar to connect IC's to antennas.

In this paper, we present an experimental characterization of microvias implemented in a multilayer printed circuit board (PCB). Using thru-reflect-line (TRL) calibration, we characterized the transmission lines connecting to the microvias and extracted the corresponding S-parameters of the microvias. Subsequently, the microvia inductance and capacitance, up to 14 GHz, were determined from the corresponding ABCD-parameters. We evaluated the measurement results with a 95% confidence interval by an uncertainty analysis and compared it to a full-wave electromagnetic (EM) simulation. Measurement and simulation show excellent agreement in both inductance and capacitance across the investigated frequency range.

This paper describes a novel packaging method for high power RF transistors, which minimizes chip to matching-network interconnect parasitic elements. Interconnect parasitics have significant importance for the development of high-frequency or harmonically-tuned power amplifiers and also for advanced power amplifier architectures such as Doherty. The demonstrated packaging method minimizes such parasitics by embedding of the chip inside the PCB laminate, enabling the development of low cost power amplifier modules for higher frequencies and wider bandwidths. The performance of an embedded device is compared to a wire-bonded device using loadpull measurements, to show the effect of the embedding on conventional high power RF transistors.

This paper presents an analytical investigation on a static capacitance of a quasi-coaxial via, which consists of a signal via and two surrounding ground vias. To determine the capacitance we propose an analytical equation derived from a modified mapping function for parallel circular conductors under the condition of a ground-signal-ground (GSG) symmetrical configuration. The validity of the derived equation as a function of via diameters and the distance between the signal via and the ground vias was examined by comparison of analytical capacitance per unit length with Q2D static numerical simulations, which results in good agreements within a few percentages of the error. Moreover, a 3D model of quasi-coaxial is designed with an existing design rule for a microvia. Its capacitance at 30 GHz is numerically extracted by full-wave electromagnetic simulation and compared to the analytical capacitance. As a result, we have observed that the difference between them is up to a few femtofarads.

A novel PCB embedded suspended stripline arrangement is proposed in order to improve the RF performance compared to classical planar technologies. The advantages are demonstrated through the design and characterization of a 2 nd -order filter at Ka-band having 4.5% fractional bandwidth (FBW). The simulated Q-factor is around 455 which is significantly higher compared to what is achievable in microstrip. The manufactured sample shows deviations in the expected range given by the manufacturing tolerances from the simulated results. However, a similar high Q-factor of 410 in Ka-band was obtained.

In this paper, a compact filter based on substrate integrated coaxial line (SICL) stubs was designed using an advanced multilayer printed circuit board (PCB) substrate. This technology is convenient to implement high-density interconnect (HDI) devices, which are dedicated to mass market and require to be compact and low cost. In addition, in order to avoid parasitic effects, HDI devices need to be shielded. The laser-drilled microvias used in the low-loss advanced multilayer PCB are the assets that allow the fabrication of compacted and shielded microwave filters. Using this technology, a third-order X-band filter based on SICL stubs was designed. The SICL topology is convenient to be used for shielded devices thanks to the outer-grounded metallization. The filter was implemented in an advanced PCB substrate composed of seven layers of Megtron 6+. The via-holes fabricated with plated through-holes or laser-drilled microvias allow implementing SICL stubs throughout the thickness of the substrate. Measurements of the X-band filter are in a good agreement with the simulation. In comparison with other compact filters, the X-band filter based on SICL stubs has a good footprint reduction while maintaining good electrical performances.

The recent developments in electronic cards such as the network equipment are characterized by the miniaturization of the board size and the increasing complexity of the layout. Because of these requirements, multi-layered printed circuit boards are commonly used and vias connecting signal lines on different layers, or integrated circuit devices to power and ground planes, are frequently used and often essential. However, a via is not an ideal transmission line. Besides, it creates discontinuities at high frequencies leading to high insertion loss degradation of signal which limits the performances of integrated circuit and systems. In this paper, the impacts of coupling between via and parallel-plates cavity on the response of microwave integrated devices are highlighted in the first part. Then, to describe the intrinsic interaction between the via transition and parallel-plate modes, the notion of parallel-plates matrix impedances is presented and new boundary conditions like open or plated through holes shielded boundaries of the cavities are introduced. Then, using this physics-based model, an intuitive equivalent circuit has been developed. Finally, the proposed approach and the equivalent circuits were validated by using comparisons with electromagnetic simulations and measurements in different scenarios.

Today ́s Electronic Industry is changing at a high pace. The root causes are manifold. So world population is growing up to eight billions and gives new challenges in terms of urbanization, mobility and connectivity. Consequently, there will raise up a lot of new business models for the electronic industry. Connectivity will take a large influence on our lives. Concepts like Industry 4.0, internet of things, M2M communication, smart homes or communication in or to cars are growing up. All these applications are based on the same demanding requirement – a high amount of data and increased data transfer rate. These arguments bring up large challenges to the Printed Circuit Board (PCB) design and manufacturing. This paper investigates the impact of different PCB manufacturing technologies and their relation to their high frequency behavior. In the course of the paper a brief overview of PCB manufacturing capabilities is be presented. Moreover, signal losses in terms of frequency, design, manufacturing processes, and substrate materials are investigated. The aim of this paper is, to develop a concept to use materials in combination with optimized PCB manufacturing processes, which allows a significant reduction of losses and increased signal quality. First analysis demonstrate, that for increased signal frequency, demanded by growing data transfer rate, the capabilities to manufacture high frequency PCBs become a key factor in terms of losses. Base materials with particularly high speed properties like very low dielectric constants are used for efficient design of high speed data link lines. Furthermore, copper foils with very low treatment are to be used to minimize loss caused by the skin effect. In addition to the materials composition, the design of high speed circuits is optimized with the help of comprehensive simulations studies. The work on this paper focuses on requirements and main questions arising during the PCB manufacturing process in order to improve the system in terms of losses. For that matter, there are several approaches that can be used. For example, the optimization of the structuring process, the use of efficient interconnection capabilities, and dedicated surface finishing can be used to reduce losses and preserve signal integrity. In this study, a comparison of different PCB manufacturing processes by using measurement results of demonstrators that imitate real PCB applications will be discussed. Special attention has be drawn to the manufacturing capabilities which are optimized for high frequency requirements and focused to avoid signal loss. Different line structures like microstrip lines, coplanar waveguides, and surface integrated waveguides are used for this assessment. This research was carried out by Austria Technologie & Systemtechnik AG (AT&S AG), in cooperation with Vienna University of Technology, Institute of Electrodynamics, Microwave and Circuit Engineering. Introduction Several commercially available PCB fabrication processes exist for manufacturing PCBs. In this paper two methods, pattern plating and panel plating, were utilized for manufacturing the test samples. The first step in both described manufacturing processes is drilling, which allows connections in between different copper layers. The second step for pattern plating (see figure 1) is the flash copper plating process, wherein only a thin copper skin (flash copper) is plated into the drilled holes and over the entire surface. On top of the plated copper a layer of photosensitive etch resist is laminated which is imaged subsequently by ultraviolet (UV) light with a negative film. Negative film imaging is exposing the gaps in between the traces to the UV light. In developing process the non-exposed dry film is removed with a sodium solution. After that, the whole surrounding space is plated with copper and is eventually covered by tin. The tin layer protects the actual circuit pattern during etching. The pattern plating process shows typically a smaller line width tolerance, compared to panel plating, because of a lower copper thickness before etching. The overall process tolerance for narrow dimensions in the order of several tenths of μm is approximately ± 10%. As originally published in the IPC APEX EXPO Conference Proceedings.

As surface finishe play allegedly a crucial role in the overall performance of RF-circuits, this paper is dedicated to evaluate the impact of four different platings, as well as plain copper, on insertion loss for commercially manufactured RF-PCBs. The selected surface finishe are Electroless Nickel Immersion Gold (ENIG), Electroless Nickel Electroless Palladium Immersion Gold (ENEPIG), Immersion Tin, and a manufacturer specifi "shiny"-gold. Although each finis has different involved processing steps, materials, and price, basically no difference in insertion loss has been measured up to 110 GHz for microstrip (MS) or conductor backed coplanar waveguides (CBCPW). Additionally, the impact of manufacturing tolerances on insertion loss has been quantified These tolerances have shown more variation on insertion loss than for all investigated surface finishes with deviations of -11 % and 14 % in insertion loss at 100 GHz of the overall mean. For obtaining accurate data, appropriate launching pad designs have been evaluated previously for conducting reliable wafer prober measurements of wet etched RF-circuits up to 110 GHz.

This paper focuses on the description of loss behavior up to 110 GHz for two commercially widely used transmission line modes, microstrip (MS) and conductor backed coplanar waveguide (CBCPW). Within this investigation special attention has been drawn to the applied manufacturing processes as each process has distinct tolerances and etching behavior. The measured data is based on a comparison of 50 Ω transmission lines manufactured on two different substrates and for two structuring processes, pattern plating and panel plating.

This paper deals with the design of Q-band filters using a low-cost multilayered Printed Circuit Board (PCB) substrate. In order to meet strong electrical specifications, the Substrate Integrated Waveguide (SIW) technique has been used to take profit of the complete build-up of the multilayered PCB. Advanced fabrication techniques of vias and micro-vias have also been developed in this project to implement 4th and 6th-order filters in this technology. The challenge here is to use a standard PCB process to design complex microwave devices that usually require accurate fabrication process and very low tolerances, especially in such frequency ranges. Based on that, two 2.8×8mm2 prototypes have been designed, simulated and fabricated on a 1mm-thick PCB made of copper and blend of high performance resin material. Regarding the results of these filters, measured insertion & return losses are in a very good agreement with the simulation while exhibiting high rejections and low footprint.