In this paper we introduce recent mathematical tools for shape description called size functions. Some features of these descriptors such as robustness with respect to noise are pointed out. A first attempt to join the theory of size functions with randomness and to develop the related statistical analysis is then presented. The resulting procedure is applied to some specific problems which arise in microlithography of electronic devices.

A potential limitation to a wider usage of the scatterometry technique for CD evaluation comes from its requirement of dedicated regular measurement gratings, located in wafer scribe lanes. In fact, the simplification of the original chip layout that is often requested to design these gratings may impact on their printed dimension and shape. Etched gratings might also suffer from micro-loading effects other than in the circuit. For all these reasons, measurements collected therein may not represent the real behavior of the device. On the other hand, memory devices come with large sectors that usually possess the characteristics required for a proper scatterometry evaluation. In particular, for a leading edge flash process this approach is in principle feasible for the most critical process steps. The impact of potential drawbacks, mainly lack of pattern regularity within the tool probe area, is investigated. More, a very large sampling plan on features with equal nominal CD and density spread over the same exposure shot becomes feasible, thus yielding a deeper insight of the overall lithographic process window and a quantitative method to evaluate process equipment performance along time by comparison to acceptance data and/or last preventive maintenance. All the results gathered in the device main array are compared to those collected in standard scatterometry targets, tailored to the characteristics of the considered layers in terms of designed CD, pitch, stack and orientation.

Optical proximity corrections are widely used in semiconductor industry to compensate non-linear effects occurring when printing features smaller than exposure wavelength. Most advanced OPC software packages simulate optical behavior starting from a physical description of illumination and projection optics, while the characterization of resist development and etch loading effects is still performed empirically, with different approaches that, generally, require the collection of a huge amount of experimental data. Due to the wide variety of target patterns, which makes conventional CD-SEM recipe creation impossible, critical dimension (CD) measurements are usually performed manually, requiring long time and, despite the attention paid while measuring, with poor guarantee of repeatability. The introduction of 193 nm resists, much more sensitive to SEM e-beam exposure if compared to 248 nm materials, required increased attention to be paid on both focusing and measuring phases in order to obtain reliable results. As well as OPC model tuning, the verification of correction effectiveness on product devices is performed almost in the same way leading to the same kind of issues.In order to overcome most of these problems ST is evaluating a new CD metrology package from Hitachi High-Technologies; this tool allows fully automatic CD measurements starting from GDS II coordinate input. The exact recognition of measurement locations is obtained through an algorithm, based on the superposition of the drawn GDS II layout to the SEM wafer images, which allows achieving high positioning accuracy.The introduction of the tool significantly reduces measuring time down to the range of normal automated CD measurement times, while guarantying improved repeatability and optimized conditions even with 193 nm resists due to the possibility of defining different structures for addressing and focusing before the measurement. This new system opens new perspectives in OPC modeling giving the opportunity of a more accurate model tuning, required by 65 nm technology node, and enables an extensive product devices OPC verification presently impossible due to time and procedure issues.

A key enabler to a successful process development and to the device functionality is the introduction of a: proper metrology framework, consisting in the selection of the "correct" tool class. for the proposed application on one hand and in the integration of the related measuring procedure into the whole process flow on the other hand.The plan for this work was focused onto the analysis of the main options for critical dimension (CD) measurements targeting to the 65nm technology node, as stated in the International Technology Roadmap for Semiconductors (ITRS) 2001 edition and in the ITRS 2002 update In order to investigate, in deeper details the actual status of each selected technique, a list of key characteristics (availability on the market, precision, resolution, interaction with target and universality) was identified and a comprehensive benchmark performed. Considered techniques include CD-scanning electron microscopy (SEM), CD-scatterometry, CD-atomic force microscopy (AFM) and "Combo" approaches (e.g. CD-SEM+CD-scatterometry, focused ion beam (FIB)+CD-SEM).Based upon the data collected during the benchmark phase, suitable procedures to be applied for a proper metrological evaluation of the 65nm node process development are presented.