Area-selective deposition (ASD) is a possible enabler for the fabrication of various future semiconductor devices. However, it remains challenging to characterize and optimize ASD processes in patterns with nanoscale dimensions, as required for semiconductor device applications. Therefore, we study Ru ASD on different types of nanopatterns on 300 mm-wafers and assess the role of the pattern geometry and density on selectivity. As selectivity is often improved by means of passivation-deposition-etch cycles, we investigate an ASD cycle consisting of passivation by (N,N-dimethylamino)trimethylsilane, deposition by (ethylbenzyl)(1-ethyl-1,4-cyclohexadienyl)Ru/O2 atomic layer deposition (ALD) and an O/Cl plasma etch. On line-space patterns with a 32 nm critical dimension, the passivation-deposition-etch cycle yields a lower defectivity level than the passivation-deposition approach for a given Ru ASD thickness. The comparison of Ru ASD on line-space and hole nanopatterns reveals the pattern-dependent selectivity, that is explained by accumulation of Ru nanoparticles at pattern edges. 300 mm-wafer uniformity is also investigated and related to reactor design. The investigation of ASD on nanopatterned 300 mm-wafers is enabled by ASD-specific developments of X-ray photoelectron spectroscopy, optical critical dimension scatterometry, and scanning electron microscopy. This research highlights the possibilities and challenges in developing ASD processes in an industrial setting.

We demonstrate electrically functional 0.099 mu m(2) 6T-SRAM cells using full-field EUV lithography for contact and M1 levels. This enables formation of dense arrays without requiring any OPC/RET, while exhibiting substantial process latitudes & potential lower cost of ownership (single-patterning). Key enablers include: 1) high-k/metal gate FinFETs with L-g similar to 40nm, 12-17nm wide Fins, and cell beta ratio similar to 1.3; 2) option for using an extension-less approach, advantageous for reducing complexity with 2 less I/I photos, and for enabling a better quality, defect-free growth of Si-epitaxial raised S/D; 3) use of double thin-spacers and ultra-thin silicide; 4) optimized W metallization for filling high aspect-ratio, >= 30nm-wide contacts. SRAM cell with SNM>10%V-DD down to 0.4V, and healthy electrical characteristics for the cell transistors [SS similar to 80mV/dec, DIBL similar to 50-80mV/V, and vertical bar V-Tlin vertical bar <= 0.2V (PMOS), V-Tlin similar to 0.36V (NMOS)] are reported.

We report on a major advancement in full-field EUV lithography technology. A single patterning approach for contact level by EUVL (NA=0.25) was used for the fabrication of electrically functional 0.186 mum2 6T-SRAMs, with W-filled contacts. Alignment to other 193 nm immersion litho levels shows very good overlay values les20 nm. Other key features of the process are: 1) use of high-k/Metal Gate FinFETs with good gate CD control: 3sigmales7 nm after double-dipole 193 nm immersion litho (NA=0.85) and 3sigmales9 nm after double-Hard Mask gate etch; and 2) use of an ultra-thin NiPt-silicide for S/D and an optimized spacers module without Si recess at dense FINs pitch. Excellent SRAM VDD scalability down to 0.6V (SNM>0.1VDD) and healthy electrical characteristics (VT, sigma(DeltaVT), I-V) for the cell transistors are obtained.

One of the main experimental setups for EUV lithography is the ASML EUV Alpha-Demo Tool (ADT), which achieves the first full-field EUV exposures at a wavelength of 13.6nm and a numerical aperture of 0.25. We report on the assessment of the baseline imaging performance of the ADT installed at IMEC, and review the work done in relation to EUV reticles and resists. For the basic imaging performance of the ADT, we have studied 40 LS patterns through dose and focus and at multiple slit positions, to extract exposure latitude and depth of focus. Measurements of reticle CD vs. wafer CD were done to determine the Mask Error Enhancement Factor (MEEF) for dense features. We also discuss the uniformity of the different features across the field, and the factors that influence it. The progress in EUV resist performance has been tracked by screening new materials on the EUV ADT. Promising resist materials have been tested on the ASML ADT and have demonstrated sub 32nm Line/Space and 34nm dense contact hole resolution. One of the main topics related to EUV reticles is reticle defectivity along with reticle defect printability. We have experimentally measured the number of wafer defects that repeat from die-to-die after reticle exposure on the ADT. To examine the wafer signature of the repeating defects, a SEM-based defect review is then conducted. We have used rigorous simulations to show that the defect signature on wafer can correspond to a relatively large ML defect, which can print as a hollow feature.

Extreme Ultraviolet Lithography (EUVL) is the leading candidate beyond 32nm half-pitch device manufacturing. Having completed the installation of the ASML EUV full-field scanner, IMEC has a fully-integrated 300mm EUVL process line. Our current focus is on satisfying the specifications to produce real devices in our facilities. This paper reports on the imaging fingerprint of the EUV Alpha Demo Tool (ADT), detailing resolution, imaging, and overlay performance. Particular emphasis is given to small pitch contact holes, which are a critical layer for advanced manufacturing nodes and one of the most likely layers where EUVL may take over from 193nm lithography. Imaging of contact holes, pattern transfer and successful printing of the contact hole level on a 32nm SRAM device is demonstrated. The impact of flare and shadowing on EUV ADT performance is characterized experimentally, enabling the implementation of appropriate mitigation strategies.

IMEC has started an EUV lithography research program based on ASMLs EUV full field scanner, the Alpha Demo Tool (ADT). The intent of this program is to help improve and establish the necessary mask and resist infrastructure, and achieve learning to prepare for the use of EUV lithography in future production of integrated circuits. The program focuses on three main projects: EUV resists, EUV reticles and assessment of the ADT performance. In this paper, the status and the progress of each of the projects is reviewed. In preparation for a resist process for the ADT, interference lithography has been used to track the progress of resist performance. Good progress in resist performance is illustrated by the ability of some materials to resolve 25nm HP. In its initial phase, the reticle project has concentrated on working with the mask and blank suppliers to assure timely availability of reticles for the ADT. An overview is given of reticle related activities, as well as first results of a defect printability study by simulation. In the ADT assessment project, simulation studies are reported aimed at the development of optical correction for flare and reticle shadowing effects. The impact of flare and shadowing effects are well understood and strategies for flare mitigation and shadowing effect correction are proposed.

About one year ago, first generation full field ArF step and scan systems (193nm) have been introduced and this has triggered a lot of activity in 193 nm lithography. Significant progress has been made in both ArF resist performance and exposure tool characterization. For introduction of 193 nm technology, a lot will depend on the maturity of the 193nm resists. Besides lithographic performance, dry etch selectivity with respect to various substrates will play an important role as well as other integration aspects such as BARC compatibility and proximity effects. In this paper, the status of ArF lithography is reviewed for the 130nm node with emphasis on the integration aspects. It will be demonstrated that the state-of-the-art 193 nm resists can already be used for integration in critical layers (gate and contacts) of typical CMOS processes. Initial results for the 100nm node using alternating phase shifting masks and quadrupole illumination look very promising for 193nm.

This paper describes extreme ultraviolet (EUV) resist screening results that have been obtained on an interference printer at the Swiss Light Source. Imaging performance of a variety of chemically amplified resists has been studied. The main focus of the work has been on evaluating ultimate resolution and exposure latitudes of various materials and on improving their process parameters. The chemically amplified resists have also been compared with non-chemically amplified PMMA. The resolution of the latter is clearly superior to that of the chemically amplified materials. Below 40–35nm half-pitch all chemically amplified materials at best show modulation in resist, a limitation that is attributed to acid diffusion. However, PMMA shows clean profiles on the interference printer down to about 20nm.

Extreme ultraviolet lithography (EUVL) is the preferred solution for the 32nm node. This paper reports on EUV resist screening results by EUV Interference Lithography, targeting at 32nm half pitch resolution. Progress in resist resolution, sensitivity and LER has been made. Champion results for chemically amplified resists are 30nm resolution, 3.8nm (3 sigma) LER and <10mJ/cm(2) sensitivity. However these were not accomplished in one single resist. The performance was compared to imaging in non-chemically amplified PMMA resist showing higher resolution and improved LER (2.5nm) at the expense of photospeed. On full field scanners the resist performance might be dominated by the flare. Possible impact of flare on resist profiles has been studied through exposures on a Micro-Exposure Tool and through contrast demodulation experiments with the interference set-up. Increasing the surface inhibition in the resist is suggested as a way to cope with the higher flare levels of full field scanners.

Since the moment immersion lithography appeared in the roadmaps of IC manufacturers, the question whether to use top coats has become one of the important topics for discussions.The top coats used in immersion lithography have proved to serve as good protectors from leaching of the resist components (PAGs, bases) into the water. However their application complicates the process and may lead to two side effects. First, top coats can affect the process window and resist profile depending on the material's refractive index, thickness, acidity, chemical interaction with the resist and the soaking time. Second, the top coat application may increase the total amount of defects on the wafer.Having an immersion resist which could work without the top coat would be a preferable solution. Still, it is quite challenging to make such a resist as direct water/resist interaction may also result in process window changes, CD variations, generation of additional defects.We have performed a systematic evaluation of a large number of immersion resist and top coat combinations, using the ASML XT: 1250Di scanner at IMEC. The samples for the experiments were provided by all the leading resist and top coat suppliers. Particular attention was paid to how the resist and top coat materials from different vendors interacted with each other. Among the factors which could influence the total amount of defects or CD variations on the wafer were: the material's dynamic contact angle and its interaction with the scanner stage speed, top coat thickness and intermixing layer formation, water uptake and leaching. We have examined the importance of all mentioned factors, using such analytical techniques as Resist Development Analyser (RDA), Quartz Crystal Microbalance (QCM), Mass Spectroscopy (MS) and scatterometry. We have also evaluated the influence of the pre- and pos- exposure rinse processes on the defectivity.In this paper we will present the data on imaging and defectivity performance of the resists with and without the use of top coats. So far we can conclude that top coat/resist approach used in immersion lithography needs some more improvements (i.e. process, materials properties) in order to be implemented in high volume manufacturing.

EUV lithography is one of the options to be introduced for the 32nm node. Early development of adequate resists and processes is required for timely introduction of EUV technology. In this paper, a screening of EUV resist materials is presented based on EUV interference lithography using transmissive gratings and a synchrotron light source. It was found that most resists are limited in resolution down to 35nm HP. One major issue is to simultaneously achieve high resolution, high sensitivity and low Line edge roughness (LER) required for the 32nm node. The results obtained with interference lithography were compared with exposures performed on a Micro-Exposure Tool (0.3 NA). Lower ultimate resolution, differences in profile but comparable exposure latitudes were seen. Interference lithography is considered to be valuable for early resist testing. Still much work is needed to push EUV resist to the levels necessary for commercialisation.

Most 157nm resist optimization to date has been done with micro-steppers, but there may be significant differences in resist profiles and process windows between micro-steppers and full field scanners. Several resists were evaluated on an ASML MS VII full-field 157nm scanner at IMEC. Focus and exposure latitudes were measured for resist lines using various feature sizes and pitches with different reticle types and illumination conditions. Resist sensitivity to post-expose bake temperature were measured. Delay effects, line-edge roughness, line slimming in a CD SEM, and etch resistance were also evaluated.

About me year ago the first full field F-2 step and scan systems have been introduced and resist process optimisation concentrating on full field issues could be started. This paper reports on the resist benchmarking, process optimisation and etch integration challenges for 157nm resists on an ASML MS VII 0.75 NA full field system. Several 157nm resists have been evaluated in terms of resolution, processing latitudes, delay stability and line-edge-roughness. Good progress in resist maturity is seen. Feasibility of sub-50nm gate patterning using 157nm resist in combination with hard masks has successfully been demonstrated.

Tight control of very small transistor gate CDs is one of the most difficult problems in advanced device patterning. Line-edge roughness on these small gate lines has become a serious issue with 193nm lithography and is only expected to worsen with 157nm and EUV lithography. Methods are needed that can minimize line-edge roughness while also enabling the patterning of small gate features. We have analyzed the use of a simple and manufacturable post-develop bake step, a 'hardbake', that controllably reduces both gate resist CDs and to line-edge roughness. Hardbake resist shrinkage is a well-known phenomena from earlier Novolak resist processing, but has not been investigated for chemically amplified resists as much as other CD slimming techniques. Our tests have been performed for different chemically amplified 193nm and EUV-type (essentially reformulated 248nm) resists. The results of our experiments show considerable potential for certain types of resists to provide gate CD control benefits from either roughness reduction or CD slimming.

157nm lithography is currently considered as the main technology for the manufacturing of critical 65nm node layers and beyond. After a number of potential show stoppers of 157nm have been removed in the last three years, the final phase of development will now start based on the first full-field step and scan exposure systems, that will be inserted in the next 6 months. This paper describes the status and progress of the IMEC 157nm program, that is aiming to remove the remaining 157nm engineering challenges. Despite the fact that the first full field scanner (ASML Micrascan VII) will ship next month to IMEC, the investigation on a number of fall-field issues already started. Results on reticle handling including vacuum ultra violet cleaning, on hard pellicle printing and on 157nm resist full field patterning are discussed in this paper.

157mn lithography is currently considered as the main technology for the manufacturing of critical 65nm node layers and beyond. After a number of potential show stoppers of 157nm have been removed in the last three years, the final phase of development will now start based on the first full-field step and scan exposure systems. This paper describes the status and progress of the IMEC 157nm program, that is aiming to remove the remaining 157mn engineering challenges. The first full field scanner (ASML Micrascan VII) is currently under installation at IMEC. The investigation on a number of full-field issues already started. Results on 157nm resist full field patterning, on reticle handling including vacuum ultra violet cleaning, and on hard pellicle printing are discussed in this paper.

Contact lithography for the 100nm generation is a difficult challenge with current layer 193nm resist processes. The SIA roadmap lists the contact hole size for 100nm lithography as 115 nm ([1]). Even with next generation very high NA (>0.7) 193 nm exposure tools, early results indicate that these contact hole sizes can not be obtained with standard processing techniques. Therefore, we have investigated the feasibility of using resist reflow to obtain small contact hole sizes.