Advanced lithography requires resolution enhancement techniques (customized illumination mode, litho friendly design), and alternative process flow schemes (double exposure, double patterning) in order to meet the requirements of the ITRS technology roadmap and to extend the applications of a full-field scanner with a 1.35 numerical aperture (NA) that represents the physical limit of water-based immersion ArF lithography. Today, one of the most interesting alternative processes uses the patterning inversion through a negative tone development (NTD) process step. Traditionally, the patterning (contacts or trenches) is done by using a dark field mask in combination with positive tone resist and positive tone development (PTD). By using a solvent-based developer (NTD) and a bright field mask, the same features can be transferred into a positive resist with the benefit of better image contrast and, consequently, better line width roughness (LWR) and resolution. In this work we have explored the potential applications of NTD for trenches and contact holes for the 45nm technology node requirements and beyond. The NTD process is a promising option considering the impact on process window, LWR, CD uniformity and defectivity. The experimental result of this alternative approach to print critical dark field levels in an advanced lithography boundary has been explored.

The laser bandwidth and the wavelength stability are among the important factors contributing to the CD Uniformity budget for a 45 nm and 32nm technology node NV Memory. Longitudinal chromatic aberrations are also minimized by lens designers to reduce the contrast loss among different patterns. In this work, the residual effect of laser bandwidth and wavelength stability are investigated and quantified for a critical DOF layer. Besides the typical CD implications we evaluate the "image placement error" (IPE) affecting specific asymmetric patterns in the device layout. We show that the IPE of asymmetric device patterns can be sensitive to laser bandwidth, potentially resulting in nanometer-level errors in overlay. These effects are compared to the relative impact of other parameters that define the contrast of the lithography image for the 45nm node. We extend the discussion of the contributions to IPE and their relative importance in the 32 nm double-patterning overlay budget.

Aggressive pitch requirements for line/space pattern devices require the usage of extreme off-axis illumination schemes to enhance the resolution of the exposure tools. These illumination schemes stress the quality of the optics because of the anisotropy of the optical paths through the lens. Moreover, the marginalities on the patterning are dramatically enhanced if two or more illumination modes are requested in the lithography process. The effects on overlay between double exposure layers exposed with different illumination settings, with one being an extreme illumination setting, will be discussed and two approaches will be addressed to compensate the resulting overlay fingerprint. The first approach optimizes the lens setup by means of a dedicated scanner option to minimize the lens effects on overlay and reduce the distortion for each layer: in this case the simulation time and the impact on other imaging parameters will be carefully evaluated. The second methodology corrects the induced misalignment by a high order modelling compensation. This approach requests the insertion of a suitable set of overlay measurement targets into the product frame to appropriately fit the distortion matching of the two layers.

Immersion Lithography is the most important technique for extending optical lithography's capabilities and meeting the requirements of Semiconductor Roadmap. The introduction of immersion tools has recently allowed the development of 45nm technology node in single exposure. Nevertheless the usage of hyper-high NA scanners (NA > 1), some levels still remain very critical to be imaged with sufficient process performances. For memory devices, contact mask is for sure the most challenging layer.Aim of this paper is to present the lithographic assessment of 193nm contact holes process, with k(1) value of similar to 0.30 using NA 1.20 immersion lithography (minimum pitch is 100nm). Different issues will be reported, related to mask choices (Binary or Attenuated Phase Shift) and illuminator configurations.First phase of the work will be dedicated to a preliminary experimental screening on a simple test case in order to reduce the variables in the following optimization sections. Based on this analysis we will discard X-Y symmetrical illuminators (Annular, C-Quad) due to poor contrast. Second phase will be dedicated to a full simulation assessment. Different illuminators will be compared, with both mask type and several mask biases. From this study, we will identify some general trends of lithography performances that can be used for the fine tuning of the RET settings. The last phase of the work will be dedicated to find the sensitivity trends for one of the analyzed illuminators. In particular we study the effect of Numerical Aperture, mask bias in both X and Y direction and poles sigma ring-width and centre.

CD control specifications for poly gate patterning are becoming tighter and tighter: latest revisions of International Technology Roadmap for Semiconductors require a CD control in the range of 2.2nm (3 sigma) for the 65nm technology node. In this scenario model-based Optical Proximity Correction methodologies, traditionally developed to address optical and resist development effects, had to face the challenge to correct post-resist processing steps with the aim to guarantee a final effective CD control within expected specifications. Complex 1D rule-based corrections, applied in the past, are no more adequate to capture complex 2D effects becoming relevant starting from 90nm node; only a more comprehensive 2D model-based approach can correctly predict, and so compensate, complex physical and chemical etch phenomena inducing CD variations. In this paper we experimentally study the impact of medium and long range etch effects on poly gate patterning, trying to identify their nature and impact on intra-die CD variations. Different innovative model-based approaches for lithography and etch effects compensation are evaluated and compared on Flash memory circuitry (90, 65 and 45 nm node) with the aim to reduce intra-die CD dispersion component. Finally the impact of local and global pattern density on etch behavior is studied in relation to different dummy placement strategies.

An enormous pressure is currently put on Resolution Enhancement Techniques to meet the deadline for the development of high density memory devices. The prevailing conviction is to consider water immersion lithography as the choice for manufacturing 45nm technology node devices. Even if a huge effort to face immersion specific issues has been done (on defectivity, micro-bubbles, contamination, overlay control, hyper NA imaging, birefringence), a technology solution to image the desired features and densities must be available till now in order to anticipate all the steps involved in the process integration before the complete assessment of the immersion infrastructure. Moreover, the forecasted solutions for 32nm and 22nm technology nodes remain uncertain, strongly depending on current and near future development of high index fluids for immersion lithography and EUV availability. These temporal lacks of technology options are forcing scanner suppliers and IC manufacturers to include also double exposure in the group of viable choices for future development. Double patterning (double exposure and double etch) is surely a fascinating solution for overcoming the physical resolution limit of k1 = 0.25 of imaging systems. Various papers in these last two years demonstrated an increasing interest in the exploration of such kind of technique to extend as much as possible ArF dry exposure tools. Though the concept of this technique is simple and well known, there are various technical issues which must be solved before moving to a real implementation in the manufacturing phase. In this paper we want to present the experimental results of the application of double patterning to the definition of a 45nm technology node Flash memory device, reaching a k1 ~ 0.20 using 193nm dry lithography. Flash memory design introduces imaging critical points in several levels: active, contacts, and first metallization. For each of these layers, a dedicated study of double exposure has been performed in order to develop a combined litho-etch process to pattern the requested features density. Different issues will be reported, related to process choices (hard mask, resist compatibility), overlay performances, OPC and layout decomposition. Experimental process windows of dedicated test masks with lines and spaces and contact holes are shown. A deep study on overlay performance and possible optimizations has been performed and will be reported. Finally, we will demonstrate that double exposure technique can be used to anticipate process integration of critical lithography steps for high density memory devices at 45nm technology node.

Double patterning (double exposure and double etch) is definitely a viable solution for overcoming the physical resolution limit of k1=0.25 of imaging systems. This article presents the overlay budget for a double patterning technique using a 45nm technology node flash memory device with k1∼0.20 and 193nm dry lithography. Adopting double exposure, the final pattern is composed of two lithography patterns within the resolution capability of the exposure tool and then combined with the double etching processes. The photoetch photoetch approach creates the overlay between the two exposures which is the most critical issue to be addressed. This article presents the adopted scanner setup, mask requirements, and efficient overlay metrology setup in order to achieve the overlay roadmap of 6nm for the 45nm technology node.

Among other memory products FLASHes are becoming a technology driver in term of design rules aggressiveness for dense structures. Upcoming revisions of ITRS roadmap forecast 45nm technology node introduction for FLASHes one year ahead (2006) compared to DRAMs (2007). In this scenario the basic development of 45nm process requires patterned samples starting from the end of 2005. Waiting for hyper-high NA ArF immersion tools availability, different RET solutions based on the existing lithography platforms have been evaluated with the aim to provide patterned samples for process modules development. Our paper is focused on 45nm node contact holes, certainly considered one of the most challenging layers in the technology assessment: various RET strategies will be briefly discussed and particular attention will be dedicated to alternating phase shift mask option. Strong PSM approach has been already proposed in the past as viable solution for 65nm node contact holes patterning using ArF tools; here we discuss problems related to its extension down to 45nm node (with dry equipments), in ultra low k(1) regime and close to the physical limit of 0.25 k(1). The paper addresses main challenges related to the application of an alt-PSM approach to a full-chip FLASH design, suggesting possible solutions for assist features generation and phase assignment. Different strategies to compensate for the well known phase imbalance phenomena have been selected by using fully rigorous 3D optical simulations. Finally preliminary printing test will be shown. Lithography performances (Minimum resolution, Process window, contact profile) will be compared with conventional RET techniques.

Optical proximity corrections are widely used in semiconductor industry to compensate non-linear effects occurring when printing features smaller than exposure wavelength. Most advanced OPC software packages simulate optical behavior starting from a physical description of illumination and projection optics, while the characterization of resist development and etch loading effects is still performed empirically, with different approaches that, generally, require the collection of a huge amount of experimental data. Due to the wide variety of target patterns, which makes conventional CD-SEM recipe creation impossible, critical dimension (CD) measurements are usually performed manually, requiring long time and, despite the attention paid while measuring, with poor guarantee of repeatability. The introduction of 193 nm resists, much more sensitive to SEM e-beam exposure if compared to 248 nm materials, required increased attention to be paid on both focusing and measuring phases in order to obtain reliable results. As well as OPC model tuning, the verification of correction effectiveness on product devices is performed almost in the same way leading to the same kind of issues.In order to overcome most of these problems ST is evaluating a new CD metrology package from Hitachi High-Technologies; this tool allows fully automatic CD measurements starting from GDS II coordinate input. The exact recognition of measurement locations is obtained through an algorithm, based on the superposition of the drawn GDS II layout to the SEM wafer images, which allows achieving high positioning accuracy.The introduction of the tool significantly reduces measuring time down to the range of normal automated CD measurement times, while guarantying improved repeatability and optimized conditions even with 193 nm resists due to the possibility of defining different structures for addressing and focusing before the measurement. This new system opens new perspectives in OPC modeling giving the opportunity of a more accurate model tuning, required by 65 nm technology node, and enables an extensive product devices OPC verification presently impossible due to time and procedure issues.

According to sizes dictated by ITRS road map, contact holes are one of the most challenging features to be printed in the semiconductor manufacturing process. The development of 90[nm] technology FLASH memories requires a robust solution for printing contact holes down to 100[nm] on 200[nm] pitch. The delay of NGL development as well as open issues related to 157[nm] scanner introduction pushes the industry to find a solution for printing such tight features using existing ArF scanner. IDEALSmile technology from Canon was proven to be a good candidate for achieving such high resolution with sufficiently large through pitch process window using a binary mask, relatively simple to be manufactured, with a modified illumination and single exposure, with no impact on throughput and without any increase of cost of ownership. This paper analyses main issues related to the introduction of this new resolution enhancement technology on a real FLASH memory device, highlighting advantages as well as known problems still under investigation.

Current 90nm Flash memory design introduces imaging critical points in several devices levels: active, poly, contacts, and first metallization. Among standard Resolution Enhancement Techniques (RET), Off axis illuminations play a fundamental role, because they are capable of providing better imaging contrast and improved process latitude in low K-1 regime with very dense structures. Starting from the simulation study of real device layer geometries, object of this work is to propose a solution in terms of illumination schemes and mask choice (binary or halftone) for each critical layer, considering K-1 around 0.35 in ArF lithography. Dedicated off axis illuminations will be compared to standard illumination modes, underlining the benefits in terms of ultimate resolution, process window and line edge roughness improvement. Experimental data confirmed the predicted gain in process robustness and, as expected, showed great line edge roughness improvement and less marginality to pattern collapse.

Contact holes are one of the most challenging features to be printed in the semiconductor manufacturing process. In 2002, Canon introduced a new technology, entitled innovative double effective-source aided lithography with single mask implemented lithographic enhancement (IDEALSmile), that was proven to be able to define contacts with high resolution and a sufficiently large through-pitch process window using a binary mask, modified illumination and single exposure, without any negative impact on throughput or any increase of cost of ownership. The technology was further improved in 2003 with the introduction of Enhanced IDEALSmile. STMicroelectronics, Mentor Graphics and Canon joined their competences to implement this technology to the production of devices. In this paper, we analyze the issues encountered and solutions developed to overcome problems raised in different areas. Experimental results are shown and compared with both expectations based on results of simulation and what is obtained by conventional approaches. Directions for future developments have been identified and are illustrated in their guidelines.

Double focal plane exposure technique has the property to increase greatly the depth of focus of a lithographic process and appears to be a solution to fulfil the requirements of the most aggressive lithographic targets. The purpose of this work is to investigate the performances of this technique and to understand its mechanisms, to be able to find the best conditions of use for a given process.A simple model based on aerial images considerations has been developed to determine the behaviours of the main lithographic parameters (DoFmax, Elmax, central dose, shape of the Bossung curves) for various values of die distance between the two focal planes. Comparisons with four experiments have been realized with different conditions (type of pattern, dimensions, wavelength, N.A. and coherence sigma). The possibility to predict the best experimental conditions (trade-off between DoF, El, resolution and LER) has been verified.

A 65nm NOR flash technology, featuring a true 10lambda2 , 0.042mum2 cell, is presented for the first time for 1bit/cell and 2bit/cell products. Advanced 193nm lithography, floating gate self aligned STI, cobalt salicide and three levels of copper metallization allow the integration with a high density and high performance 1.8V CMOS