Optical proximity corrections are widely used in semiconductor industry to compensate non-linear effects occurring when printing features smaller than exposure wavelength. Most advanced OPC software packages simulate optical behavior starting from a physical description of illumination and projection optics, while the characterization of resist development and etch loading effects is still performed empirically, with different approaches that, generally, require the collection of a huge amount of experimental data. Due to the wide variety of target patterns, which makes conventional CD-SEM recipe creation impossible, critical dimension (CD) measurements are usually performed manually, requiring long time and, despite the attention paid while measuring, with poor guarantee of repeatability. The introduction of 193 nm resists, much more sensitive to SEM e-beam exposure if compared to 248 nm materials, required increased attention to be paid on both focusing and measuring phases in order to obtain reliable results. As well as OPC model tuning, the verification of correction effectiveness on product devices is performed almost in the same way leading to the same kind of issues.In order to overcome most of these problems ST is evaluating a new CD metrology package from Hitachi High-Technologies; this tool allows fully automatic CD measurements starting from GDS II coordinate input. The exact recognition of measurement locations is obtained through an algorithm, based on the superposition of the drawn GDS II layout to the SEM wafer images, which allows achieving high positioning accuracy.The introduction of the tool significantly reduces measuring time down to the range of normal automated CD measurement times, while guarantying improved repeatability and optimized conditions even with 193 nm resists due to the possibility of defining different structures for addressing and focusing before the measurement. This new system opens new perspectives in OPC modeling giving the opportunity of a more accurate model tuning, required by 65 nm technology node, and enables an extensive product devices OPC verification presently impossible due to time and procedure issues.

Scanning Electronic Microscopes (SEM) are widely used either for cross‐section measurement (process development) or for top‐down CD measurement (production). ITRS roadmap for CD and overlay metrology points out some difficult challenges for next technology nodes. Up to now, we remained confident respectively in SEM capability and in bright field microscopy for next node requirements. Today, the limit of 0.1 micron is crossed and new requirements are stated for new 300 mm fabs. Demands arise for tighter precision, complex profile metrology and fully non‐destructive control for in‐line and integrated tools. Scatterometry is an alternative solution for CD and overlay metrology, recently introduced in fabs. We propose to review the capability of scatterometry actually demonstrated in fab and potential extensions targeting 65nm technology node. The use of optical CD tools in a production environment has also been assessed for various applications. Finally, an overview of capability extension will be given.

A key enabler to a successful process development and to the device functionality is the introduction of a: proper metrology framework, consisting in the selection of the "correct" tool class. for the proposed application on one hand and in the integration of the related measuring procedure into the whole process flow on the other hand.The plan for this work was focused onto the analysis of the main options for critical dimension (CD) measurements targeting to the 65nm technology node, as stated in the International Technology Roadmap for Semiconductors (ITRS) 2001 edition and in the ITRS 2002 update In order to investigate, in deeper details the actual status of each selected technique, a list of key characteristics (availability on the market, precision, resolution, interaction with target and universality) was identified and a comprehensive benchmark performed. Considered techniques include CD-scanning electron microscopy (SEM), CD-scatterometry, CD-atomic force microscopy (AFM) and "Combo" approaches (e.g. CD-SEM+CD-scatterometry, focused ion beam (FIB)+CD-SEM).Based upon the data collected during the benchmark phase, suitable procedures to be applied for a proper metrological evaluation of the 65nm node process development are presented.

Commercially available photoresists for 193nm litho technology still suffer of undesired phenomena, which could eventually limit the stability of critical layer processing. Also standard CD-SEM inspection has its impact on the overall litho budget, as the interaction between the primary electron beam and the photoresist locally modifies target dimension. The reduction of this effect can be important to preserve geometrical and also electrical characteristics of the chip, as the local variation of the CD is detectable also after target etching and resist removal. In this paper different strategies to reduce its impact onto production wafers are investigated and compared. By applying a combination of these techniques, CD local modification can be lowered up to 75%.