Reduced Pressure Chemical Vapor Deposition (RP-CVD) Epitaxy bellow 600 °C is studied for 3D sequential integration [1] where cyclic deposition is needed. Another approach can be useful with Si epitaxy at temperature bellow 600 °C : the deposition of amorphous Si on dielectric during non-selective epitaxy combined with solid phase epitaxy regrowth (SPER) to extend the monocrystalline area. Indeed, using temperature above 600 °C during non-selective epitaxy, a polycrystalline Si film is formed on dielectric. This technique has been used in heterojunction bipolar transistor for the non-selective base deposition [2] and can also be used to ensure a fully monocrystalline emitter. Si:As process has been developed at 550 °C using disilane (Si2H6) as Si precursor and Arsine (AsH3) for As precursor. At this temperature, disilane is mandatory to ensure a sufficient growth rate. The disilane process will be compared to a process of reference, using silane (SiH4) precursor at 620 °C. The As dopant concentration targeted is between 1x20 at.cm-3 and 5x20 at.cm-3. Finally, the dopant diffusion is controlled on non-productive Si(100) wafer (NPW), without pattern, by SIMS for both processes before and after thermal budget (720 °C, 1 h + high temperature Spike anneal) to simulate the thermal budget undergone by the emitter. Thanks to the ASTAR system [3] from NanoMEGAS, the crystal orientation and phase maps of the emitter are extracted for both processes (Fig 1.a). ASTAR system is based on the Automated Crystal Orientation Mappings technique used on a Transmission Electron Microscope (ACOM-TEM). With silane precursor, a poly-emitter is generated whereas the emitter is fully monocrystalline with disilane. The amorphous deposition coupled with SPER ensure a fully monocrystalline emitter. SIMS analysis have been performed and show abnormal diffusion of As with disilane process. To understand the causes of the diffusion, both Si:As processes have been reproduced on NPW by full sheet epitaxy. The abnormal diffusion is still observed with the disilane process (Fig 1.b). Compared to diffusion length extracted from [4] (19nm) the diffusion of As is enhanced. Moreover, As enhanced diffusion occurs for low temperature thermal budget (Fig. 1.c). Historically, defects generated from implantation are known to enhance the diffusion length of the dopant. This phenomenon is called Transient Enhanced Diffusion (TED) and it has been studied and observed from dopant implantation [5]. The implantations generate a supersaturation of interstitials defects (such as auto-interstitial) which enhance the dopant diffusion for low temperature thermal budgets. This is a transient effect because the enhanced diffusion occurs in a short time [5]. In our case, several anneal at 720 °C were applied on the disilane Si:As layer from 1 h to 24 h (Fig. 1.d). Most of the diffusion occurs after the annealing at 720 °C, 1 h. These results highlight the transient effect of the As diffusion using disilane process. With the disilane process, TED of As occurs. Indeed, enhanced diffusion of Arsenic appears only for low temperature annealing and the effect is also transient. Compared to implantation which generates defects during the bombardment, low temperature epitaxy generates defects when the growth rate is too high. The molecules from the gas phase are adsorbed on the surface and break down on atoms (called adatom). The adatoms diffuse on the surface to find a suitable site. During low temperature epitaxy, when the growth rate is too high, the adatom don’t have enough time to diffuse on a suitable site and generate defects. Finally, dopant profile analysis will be completed by atomic force microscopy (AFM) and sheet resistance measurement. The AFM will provide an evolution of the surface topography with the annealing. The sheet resistance, coupling with SIMS, will help to extract the deactivation of dopant. The causes of the TED from disilane process at 550 °C will be discussed and experimental results will be provided. [1] L. Brunet et al., IEEE International Electron Devices Meeting (IEDM), 2018 [2] Holger Rücker and Bernd Heinemann, Semicond. Sci. Technology, 2018 [3] A. Valery, Doctoral dissertation. Université Grenoble Alpes, 2017 [4] S. W. Jones, "Diffusion in silicon". IC Knowledge LLC, 2008 [5] S. C. Jain, et al., Journal of applied physics, 2002 Figure 1

Optimization of Heterojunction Bipolar Transistors is crucial for improving RF capabilities of modern BiCMOS technologies. Fully-implanted collectors are meant to reduce fabrication complexity and Super Shallow Trench Isolation (SSTI) structures are used to reduce the consequent high base–collector capacitance. Ion implantation can induce lattice defects in silicon and carbon plus phosphorus co-implantation helps reducing them, even if it cannot avoid formation of dislocations generated by bad recrystallization of the implantation-induced amorphous silicon layer. Defects within the device are known to impact functionality and must be avoided. Understanding of the interaction between implantation-induced amorphization and substrate stress due to isolation structures is required for ensuring a reliable integration. Amorphous layer positioning with respect to substrate surface is investigated as the main defect-generation mechanism. Incomplete surface amorphization is shown to induce multiple types of dislocations affecting device functionality. Total surface amorphization ensures almost ideal current characteristics. Silicon clusters appear at high phosphorus/carbon ratios with no impact on functionality. Stress induced by isolation structures is not responsible for dislocations generation but modulates speed of the recrystallization fronts, impacting defects placement.

In this paper, epitaxial growths or depositions were performed, in 300 mm RP-CVD chambers, on two types of templates: N-type Si substrates or poly-Si/oxide/ P-type Si substrates. SiH4+HCl+H2 and SiH2Cl2+HCl+GeH4+H2 chemistries were used to deposit Si and SiGe layers between 675-750°C and 10-20 Torr on such wafers. Monocrystalline and polycrystalline growth kinetics were similar for intrinsic SiGe. Meanwhile, growth kinetics and boron incorporation were different for mono-Si:B, mono-SiGe:B, poly-Si:B and poly-SiGe:B layers. While the impact of B atoms is well documented in monocrystalline layers, it is still poorly understood for polycrystalline layers. An attempt has therefore been made to quantify it by measuring the poly-structure, with a focus on the poly-grains size and the number of grain boundaries. A lattice contraction coefficient β = - 9.82 * 10-24 cm3 has otherwise been extracted from an in-depth study of the incorporation of B atoms into substitutional sites of the SiGe epitaxial lattice.

Monocrystalline SiGe alloys can be used instead of monocrystalline Si in order to increase the performances of devices such as heterojunction bipolar transistors (HBTs) [1]. The epitaxial growth of blanket, monocrystalline SiGe layers on Si with a dichlorosilane + germane + hydrochloric acid chemistry was extensively investigated in the literature [2,3]. Similarly, a switch from polycrystalline Si to polycrystalline SiGe can be favorable, for instance, in Complementary-MOS (C-MOS) devices [4,5]. However, the blanket growth by Reduced-Pressure Vapor Deposition (RP-CVD) of polycrystalline Si and SiGe has not been systematically investigated. We have thus performed a one-to-one comparison in terms of growth kinetics and electrically active dopant incorporation between blanket monocrystalline and polycrystalline Si(:B) and SiGe(:B) layers. Epitaxies or depositions were performed, in 300 mm RP-CVD chambers, on two types of templates (Fig.1): i) N-type Si substrates (Fig.1(a)) and ii) poly-Si/oxide/ P-type Si substrates (Fig.1(b)). The poly-Si layer in stack 1.(b) was obtained thanks to amorphous Si deposition followed by annealing at 750 °C, resulting in a poly-Si film. SiH4+HCl+H2 (named Process 1) and SiH2Cl2 (DCS)+HCl+GeH4+H2 (named Process 2) chemistries were used to deposit Si and SiGe layers between 675-750 °C and 10-20 Torr. Monocrystalline and polycrystalline SiGe growth kinetics for two process conditions: i) 750 °C, 10 Torr with a HCl partial pressure of 0.05 Torr and ii) 725 °C, 10 Torr, with a HCl partial pressure of 0.06 Torr, were similar to that in the literature [1-3, 6-8]. As already shown for monocrystalline layers, there was an increase of the intrinsic SiGe growth with the germane partial pressure and the temperature. Meanwhile, it was reduced when adding HCl (Fig.2). Very similar growth rates and evolutions were however obtained whatever the crystalline state of the layers. When diborane was added the gaseous mixture, different behaviors were evidenced depending on i) the crystallinity and ii) the stoichiometry. The Si:B and SiGe:B growth rates increased with the B2H6 flow whatever the chemistry (Fig.3). This was due to a hydrogen desorption increase on boron surface sites [5,10-11]. Growth rates were otherwise higher for monocrystalline than for polycrystalline layers. The electrical resistivities of c-Si:B and c-SiGe:B layers were one decade lower than those of poly-Si:B and poly-SiGe:B layers, however (Fig.4). Resistivity values were otherwise higher for c-Si:B than for c-SiGe:B. This was likely due to i) a better incorporation of B atoms into SiGe than in Si [3,8,9] and ii) a better hole mobility in SiGe [10]. An opposite behavior was observed for polycrystalline layers, with higher resistivities for poly-SiGe:B than for poly-Si:B. We otherwise had similar resistivity evolutions as the partial pressure of diborane Pp(B2H6) increased for all types of layers. A decrease was observed first, followed by a resistivity plateau then some resistivity re-increase for really high diborane flows. Such a phenomenon was already observed for monocrystalline layers and was explained by a crystalline quality degradation [3,8,9] that reduced the hole mobility. A similar behavior was assumed for poly-layers, with a morphological transition to the amorphous phase [11,12]. Top-view Scanning Electron Microscopy (SEM) images (Fig. 5) confirmed the morphological evolution of c-Si:B, poly-Si:B, c-SiGe:B and poly-SiGe:B as the diborane partial pressure increased. New data points for c-SiGe and c-SiGe:B will also be provided for other process conditions. For intrinsic layers, we will show that Refs. [1,2] x2/(1-x) = n×(F(GeH4)/F(SiH2Cl2)) relationship between the Ge concentration x and the germane over dichlorosilane mass-flow ratio is also valid at 10 Torr, with n = 3 at 700 °C with a F(SiH2Cl2)/F(H2) Mass-Flow Ratio (MFR) of 0.005 and a F(HCl)/F(H2) MFR of 0.006. Various characterization techniques were also used to determine the concentration of substitutional Boron atoms in SiGe:B layers and the lattice contraction coefficient (β = 9.11×10-24 cm3). The value of the latter, which is most useful to assess the compressive strain compensation by small boron atoms in SiGe layers, will be compared to literature values. [1] J. Appl. Phys. 88 (2000) 4044 [2] J. Crystal Growth 305 (2007) 113 [3] J. Crystal Growth 310 (2008) 62 [4] J. Microelec. Sys. 16 (2007) 68 [5] International Electron Devices Meeting (1991) 567 [6] Appl. Phys. Lett. 56 (1990) 1275. [7] S. Chang et al., ECS Proceedings 87–8 (1987) 122 [8] J Mater Sci: Mater Electron (2007) 18:747 [9] ECS Trans. 75, 8 (2016) 265 [10] Mater. Sci. Eng. B 114–115 (2004) 318 [11] Appl. Phys. Lett. 66 (1995) 195 [12] ECS Trans. 35, 30 (2011) 45 Figure 1

Emitter resistivity should be optimized to increase the electrical performances of bipolar transistors. A non-selective Si:As deposition at temperature higher than 600 °C is currently used to fabricate such emitters: poly Si:As grows on dielectrics whereas monocrystalline Si:As grows on Si. A fully monocrystalline material would be needed to reduce the emitter resistivity, however. Therefore, a new process performed at 550 °C has been developed with Si2H6 as the Si precursor. Emitter mono-crystallinity is achieved by coupling amorphous deposition on dielectrics and solid phase epitaxy regrowth. The crystallinity of the structure has been checked by ACOM-TEM. With the Si2H6 process, an unusual diffusion of As is observed and has been reproduced on blanket wafers. The study on blankets wafer highlights that the diffusion is enhanced during a period: no enhanced diffusion occurs between 10 h and 24 h annealing at 720 °C. For the first time, transient enhanced diffusion of As is observed after low temperature epitaxy.