A SPAD (Single Avalanche Photo Diode) Physics based model including all key features to develop and to optimize a pixel design is described in this study. Model Hardware Correlations on Figures of Merits are demonstrated in CMOS technology. The predictability of this model as well as its accuracy and reliability in terms of transient simulations are highlighted.

A Photodiode model including all key features to develop and to optimize a pixel or a photonics design is described in this paper. Model hardware correlation on Figures of Merits are demonstrated on a high-speed photodiode in Photonics technology. The predictability of this model as well as its accuracy and reliability are highlighted.

An innovative and accurate model using both MOSVAR-compact model and external lumped components is presented to address design accuracy improvements needs for RF and mmW applications. In addition, a dedicated automated modeling extraction method is described. These two features are tested and validated on 2 types of R F/m m W varactors. Significant improvement in accuracy is obtained on a large geometrical range for capacitance, while guaranteeing accurate leakage and temperature dependency modeling. Models are available for several simulators demonstrating portability capabilities for MOSVAR.

This paper presents a design-oriented MOS transistor model that uses only 7 parameters for analytically describing the MOSFET behavior. Based on the inversion charge, it accounts for the most relevant short-channel effects in advanced technologies. The model provides analytical relations for the transconductances, output conductance, and nonlinearities of the transistor for simple analytical circuit design. The model is validated using the 28nm FD-SOI technology from STMicroelectronics and is compared to a state-of-the-art 4-parameter model to demonstrate the advantages of the proposed model for RF/analog design purposes.

The Partially Depleted Silicon On Insulator (PDSOI) transistor is used for a wide range of applications, in particular for RF. The current standard compact model of SOI-like transistor does not take into account a bias dependence of the body resistance. Building upon our experience developing the PSP model, we propose here a stand-alone Verilog-A model of body resistance. This nonlinear resistance model is validated against 3D TCAD and 65nm PDSOI experimental data.

With the maturity of CMOS technologies and their use for various digital, analog and RF applications, some additional effects must be modeled or enhanced to improve the accuracy of SPICE models. Non-Quasi-Static (NQS) effect is one of them; this paper proposes here to present a pragmatic NQS approach adapted to L-UTSOI model and compared to TCAD simulation, segmented model and experimental data.

The use of an addressable array test structure designed on a 28 nm FD-SOI technology for the variability analysis of static, low frequency noise (LFN) and Random Telegraph Noise (RTN) matching is presented. The experimental setup was validated, and a statistical analysis of the above electrical quantities is provided. Using such structures, combined with a switching matrix, local and global variability analysis can be performed while significantly increasing the number of samples, thus enabling a better description of the variations in LFN and RTN, especially when RTN signatures can be scarce. We show that local variations dominate the noise variability compared to global variations.

This paper presents a 7-parameter analytical model of the MOS transistor based on the inversion charge targeted at the development of simplified analytical circuit design methodologies that take into account the physics of the MOS transistor. The proposed design-oriented model allows for the first time to describe both the main short-channel effects of advanced nanometric technologies and the dependence of the transistor drain current on the drain voltage, while the model remains valid for all bias regimes (from weak to strong inversion) and for all operating regions (linear and saturated). A simple procedure based on the device physics is proposed to estimate the transistor model parameters for a given technology. Furthermore, analytical expressions of the current derivatives are developed targeting different design scenarios. The accuracy of the proposed model is validated by direct comparison to silicon measurements of N-MOS transistors in 28 nm FD-SOI technology for channel width of $1~\mu \text{m}$ and channel lengths of 30 nm, 60 nm and 150 nm, and also to simulations performed with an industry-standard compact model.

RF Front-End Modules (FEM) for both smartphones and infrastructure are today deployed thanks to several technologies (GaAs, GaN, LDMOS, SiGe and RFSOI). RFSOI technology has already completely replaced GaAs for RF switches integration, but due to its very good cost/performances trade-off, RFSOI technology is also a good candidate to enable RF FEM System On Chip (LNA, PA and RF Switch on the same die). We present in this paper the development on 300-mm wafer of a cost-optimized 40-nm PDSOI technology targeting 5G wireless networks from sub-6 GHz up to mmW frequencies. Elementary devices and circuits measurements are reviewed to illustrate achievable performances.

This study analyses the effect of test structure design for on-wafer TRL calibration of 28nm FD-SOI MOSFETs upto 110 GHz. Two different calibration kits are designed with and without continuous ground plane and their effect on the extracted transistor parameters are studied in terms of the measurement discontinuities encountered. Measurement results are discussed in conjunction with electromagnetic (EM) co-simulations, which use the small-signal equivalent circuit model of transistor along with the 3D models of the probes and test structures. The electric field coupling between the probes is visualised in each case and conclusions are drawn.

This paper presents a simple and efficient methodology for LNA design which uses the inversion level of the transistor as a design parameter in order to optimize the energy efficiency. The method uses a simple but accurate 7 parameter-based model valid in all regions of operation and allows an accurate preliminary sizing based on an analytical study. The proposed model describes the main short-channel effects in advanced technologies and allows an analytical evaluation of the LNA nonlinearity. A use case using a 28 nm FD-SOI technology is proposed to reflect that the methodology is well suited for designs at weak to moderate inversion level in an advanced technology for which simulation-based studies are often used for early sizing.

In this work, a new statistical detection method of Random Telegraph Noise (RTN) in the frequency domain is presented. An algorithm for the automated detection of Lorentzian spectra in the noise power spectral density (PSD) of a device is proposed, which enables the processing of a large amount of experimental data. Using 40 nm Bulk CMOS technology as a test vehicle, we demonstrate that the detection of Lorentzian spectra in the noise PSD allows an easier, faster, and often more precise detection of RTN presence compared to the time domain detection.

Maximum oscillation frequency (f MAX ) of mmwave transistors is one of the key figures of merit (FOMs) for evaluating the HF-performance of a given technology. However, accurate measurements of f MAX are very difficult. Determination of f MAX is significantly affected by the measurement uncertainties in the admittance (y) parameters. In order to get rid of the random measurement error and to obtain a reliable and stable f MAX value, the frequency dependent y-parameters are described by rational functions formulated from the small-signal hybrid π-model of the transistor under investigation. The parameters of these functions are determined following a least square error technique that minimizes the functional error with the measured data. The approach is especially useful for a fast and reliable evaluation of f MAX value. Devices from two different SiGe and an FDSOI (Fully Depleted Silicon On Insulator) MOS technology are measured and stable f MAX values are estimated following this approach.

This work focuses on the characterization of 28nm FD-SOI NMOS transistors, in order to study the effect of the calibration techniques employed and the overall measurement environment in the frequency range of 1 - 110 GHz. Comparison is made between the off-wafer SOLT calibration and on-wafer TRL calibration, both followed by de-embedding. The transistor as well as the Open and Short de-embedding structures are characterized to extract the transistor RF figure of merit fT, and the compact model parameters C-gg and g(m). Measurements are also repeated with different RF probes (Cascade Infinity and Picoprobe). The results obtained are compared to simulations with the Leti-UTSOI2 model for FD-SOI and conclusions are drawn.

The Fully-Depleted Silicon On Insulator (FDSOI) technologies are deployed for a wide range of applications (digital, analog, RF, etc.) requiring a large variety of MOS transistors. These transistors are defined by several dedicated specificities such as their threshold voltage or their gate oxide thickness. Usually, the surface potential (SP) based compact model of FDSOI MOSFET supposes an undoped channel with metal gate in front and back contact [1–3]. These models are not sufficiently accurate for real devices; thus, in the modern compact models [1–3], a lot of parasitic effects must be included such as the substrate depletion. This paper describes the recent improvements of L-UTSOI standard model, with the introduction of the poly-depletion effect and an enhanced model of the substrate doping effects. These model extensions are validated against silicon experimental data and available in the latest official model release.

With the maturity of CMOS technologies and their use for low power various analog and digital applications, some additional effects must be modeled or enhanced to improve the accuracy of SPICE models. Indeed, with the decrease of supply voltages/currents and the use of the back bias in Fully-Depleted Silicon On Insulator (FDSOI) technologies, the devices operate close to the weak-moderate inversion, where gm/Id Figure is impacted by effects like the depletion of source/drain electrodes and the parasitic currents such as Impact ionization current in moderate inver-sion and Gate Leakage current in weak inversion, can have a significant impact on the model accuracy. This paper describes the latest significant improvements of L-UTSOI model (formerly Leti-UTSOI) related to version 102.4. These model extensions are validated against Silicon experimental data.

The gate leakage current in advanced FD-SOI devices are investigated using systematic measurements on multiple geometry devices from 14 nm node. A simple model with an equivalent trapezoidal barrier based on WKB approximation is introduced and verified on the different measurements. The wafer level variability of the leakage current is explored using statistical modelling and the simple model for gate leakage current. The pure physical sources of variation are identified and the scaling trends of the standard deviations of the sources are analysed. The methodology and models have been validated also on 28 nm node devices.

Device level variability in a single wafer has been analysed using electrical test data from dedicated low leakage addressable array test structures. The variability has been studied in terms of the drain current. Measurement setup and data processing techniques were used to separate different types of variability. A statistical modelling approach was used to model the measured variability and a unique set of physical sources of variability has been identified and quantified for the different types of variabilities. Monte-Carlo simulations using the calibrated Leti-UTSOI compact model and the quantified sources of variability as normal random variables have been verified to reproduce the measured variances.