Partially depleted (PD) SOI technologies are mature for production of high speed, low power microprocessors. The paper highlights several challenges found during the course of development of a PD 90nm SOI technology. The technology features highly advanced transistors using strained Si and a gate length of sub 45nm with a nine layer low k backend. By optimizing the strained Si process and overall processing we have achieved yield equal than conventional technologies but with higher performance. The technology was developed for the 64bit Opteron and Athlon 64 microprocessors.

Highly customizable and scaleable scribe-based circuits have been demonstrated as effective tools for gathering process window response curves and variations data not easily obtained through standard electrical test structure approaches or inline characterization. This work demonstrates the feasibility of using these types of circuits in design rule definition, mask validation, lithography margining, and OPC qualification and refinement. Finally, given their small form factors, they are easily adopted in high-volume manufacturing environments as process monitoring tools

Gate length (L/sub GATE/) scaling to reduce CMOS delay is becoming problematic due to high gate currents from thin gate dielectrics, process induced L/sub GATE/ variation, and high channel dopings that reduce carrier mobility. These issues have led to tailoring of transistor architecture components and a "multiple everything" approach (e.g. multiple oxides, multiple threshold voltages) for both digital and analog circuit elements. Higher mobility transistor structures are desirable because transistor delay can be reduced without the penalties of gate current or L/sub GATE/ variation. Individual tailoring of source and drain is an area where further gains can be realized, and is the subject of this work. Transistors with asymmetric halo have been developed and, for the first time to our knowledge, implemented in a highly complex, seventh generation microprocessor with >10/sup 7/ transistors. Opportunities and challenges for both digital and analog design with asymmetric transistors are explored.

For the first time, tensile and compressively stressed nitride contact liners have been simultaneously incorporated into a high performance CMOS flow. This dual stress liner (DSL) approach results in NFET/PFET effective drive current enhancement of 15%/32% and saturated drive current enhancement of 11%/20%. Significant hole mobility enhancement of 60% is achieved without using SiGe. Inverter ring oscillator delay is reduced by 24% with DSL. Overall yield for the DSL process is comparable to that of a similar technology without DSL. Single and multi-core SOI microprocessors are being manufactured using the DSL process in multiple, high-volume fabrication facilities.