We have extensively studied stress enhancing techniques to increase channel mobility starting at the 130 nm technology node and continued this towards the 45 nm node. Stressed overlayers and spacer materials, strained SOI substrates, embedded SiGe and SiC layers and their proximity effects, the impact of different silicides, stress memorization and compatibility with laser and flash anneals have been investigated. The integration of abovementioned techniques into a CMOS flow resulted in an outstanding pMOS and nMOS performance improvement, no reliability issues and no impact on short channel behavior.

Partially depleted (PD) SOI technologies are mature for production of high speed, low power microprocessors. The paper highlights several challenges found during the course of development of a PD 90nm SOI technology. The technology features highly advanced transistors using strained Si and a gate length of sub 45nm with a nine layer low k backend. By optimizing the strained Si process and overall processing we have achieved yield equal than conventional technologies but with higher performance. The technology was developed for the 64bit Opteron and Athlon 64 microprocessors.

With the need to reduce vertical and lateral device dimensions, submelt laser and flash anneal either with or without prior spike rapid thermal anneal (sRTA) has recently attracted attention. It combines improved active area activation with reduced gate poly depletion for a process that is essentially free of additional diffusion. This paper will focus on process integration issues during implementation into 90 and 65 nm SOI logic technologies: Transistor parameter fluctuation and pattern effects, power density limitations and the impact on the reliability of ultra-thin gate oxides, compatibility with new materials such as SiGe, transistor scaling and performance enhancement