Data filtering and regression methods are compared in the context of PV plant capacity testing analysis, specifically for cloudy sites, with the goal of decreasing the amount of data required to produce a reliable AC output power capacity rating. Robust regression methods such as least absolute residual and bisquare are applied in contrast to the ubiquitous least squares regression method. Additionally, datasets are filtered using three different irradiance thresholds. Analysis is performed on data from individual days; cumulative datasets are built by adding daily data with the best agreement to the model.

A scenario for future silicon photovoltaics is to use wafer-based solar cells with a thickness below 100μm. A way to realize this scenario is the merging of cell and module processing, with thin wafers processed while attached to the superstrate glass. One of the challenges for this type of processing is the achievement of high performing surface passivation, i.e., with surface recombination velocities below 10cm/s. In this paper, a detailed explanation for lifetime degradation on wafers bonded to glass by means of silicone is proposed. The degradation is due to cyclic silicone molecules outgassing during a-Si:H deposition from the adhesive used to bond the wafers. The cyclic molecules are incorporated in the a-Si:H layer and modify the amorphous silicon network. By the application of specific outgassing conditions before a-Si:H deposition, a significant amount of cyclic molecules is removed from the adhesive. Non-degraded a-Si:H layers and surface passivation comparable to standalone wafers are obtained, as shown with measures of lifetime and solar cell open circuit voltage.

A design concept supported by numerical device modeling is presented for a p-type IBC cell with screen-printed aluminum for both contact polarities. Applying such a design to Cz silicon appears to offer cell efficiency exceeding 20%. The key enabling feature for this design is cleaving each cell into strips held together by tape. These strips are then connected electrically in series using extrusion printing after the strips are laminated to the module glass. The resulting module technology is called SPLICE, for “Screen Printed Locally Interdigitated Contact Elements”.

ABSTRACTPorous silicon plays an important role in the concept of wafer‐equivalent epitaxial thin‐film solar cells. Although porous silicon is beneficial in terms of long‐wavelength optical confinement and gettering of metals, it could adversely affect the quality of the epitaxial silicon layer grown on top of it by introducing additional crystal defects such as stacking faults and dislocations. Furthermore, the epitaxial layer/porous silicon interface is highly recombinative because it has a large internal surface area that is not accessible for passivation. In this work, photoluminescence is used to extract the bulk lifetime of boron‐doped (1016/cm3) epitaxial layers grown on reorganised porous silicon as well as on pristine mono‐crystalline, Czochralski, p+ silicon. Surprisingly, the bulk lifetime of epitaxial layers on top of reorganised porous silicon is found to be higher (~100–115 µs) than that of layers on top of bare p+ substrate (32–50 µs). It is believed that proper surface closure prior to epitaxial growth and metal gettering effects of porous silicon play a role in ensuring a higher lifetime. Furthermore, the epitaxial layer/porous silicon interface was found to be ~250 times more recombinative than an epitaxial layer/p+ substrate interface (S ≅ 103 cm/s). However, the inclusion of an epitaxially grown back surface field on top of the porous silicon effectively shields minority carriers from this highly recombinative interface. Copyright © 2013 John Wiley & Sons, Ltd.

With crystalline silicon technology around in commercial products for over 30 years and still dominating the PV market for the foreseeable future, it is important to consider how this technology can be improved to cope with the increasing demand for lower cost. This paper builds on a concept proposed by imec, integrated-interconnect-module (i(2)-module), to merge current crystalline silicon cell and module technology with module-level thin-film technology. It investigates, in particular, how hydrogenated amorphous silicon (a-Si:H) layers can be deposited on wafers that are bonded to a glass superstrate, to provide a low-temperature (heterojunction) approach for passivation and emitter formation in this concept.First, the concept is introduced, together with its context and motivation for a-Si:H heterojunctions. Then, the experiments are described. Starting from screening trials on temporarily and permanently bonded wafers, the plasma-enhanced chemical vapor deposition (PECVD) a-Si:H deposition process is optimized by shielding the adhesive from the plasma, resulting in comparable surface passivation quality between bonded samples and standalone wafers. Finally, first attempts toward integration into solar cell devices are reported, resulting into efficiencies above 18%. (C) 2013 Elsevier B.V. All rights reserved.

In order to test whether the lab facilities of Hanwha Solar America in Santa Clara are compatible with high-efficiency processing, we commissioned ISFH to fabricate small-area crystalline-silicon high-efficiency solar cells based on the RISE process. We reach efficiencies exceeding 23%, observed no statistically significant difference between the cells processed completely at ISFH and the cells partly processed at Hanwha, and conclude that the facilities are compatible with high-efficiency processing. Meanwhile, we analyze the performance reached by the cells in the different splits of the experiment. We find that a passivation of the n-type surface based on SiO2 improves the open-circuit voltage, but suffers from a lower (pseudo-) fill-factor compared to an Al2O3 passivation layer. We also observe that increasing the emitter width increases the open-circuit voltage thanks to a lower saturation current but reduces also the fill-factor because of increased majority-carrier resistivity.

Extensive low-temperature (T) electron spin resonance studies (ESR) have been carried out on as-fabricated, vacuum annealed, and irradiated single crystalline arrays of Si nanowires (NWs) with a top diameter of 5 nm produced by top down etching into (100)Si, finally thinned down by high-T oxidation. This reveals the presence of a substantial inherent density of Pb0 (Si3≡Si•) interface defects (charge trapping and recombination centers) quite above standard thermal values, leaving NW-Si/SiO2 interfaces of reduced electrical quality with, consequently, negative influence on the efficiency of passivation of defects by H. The inherent interface quality appears limited by the wire-narrowing thermal oxidation procedure. Vacuum annealing (≈610 °C) is found to generally reduce, to more or lesser extent, the Pb0 density to a common value over all samples studied, which result directly counters the presence of inadvertent passivation of defects by H. Rather, the anneal appears to effectuate some interface healing. Short term (\lesssim2 h) UV and VUV (10.02 eV) irradiation has little effect in general, with perhaps some weak increase of Pb1 defects induced by UV photons. On the basis of the observed E'γ defect properties, the chemical vapor deposited Si NW inter space filling Si oxide (200 °C) is found to be OH enriched.

In order to relax the mechanical constraints of processing thin crystalline Si wafers into highly efficient solar cells, we propose a process sequence, where a significant part of the process is done on module level. The device structure is an interdigitated-back-contact cell with an amorphous silicon back surface field. The record cell reaches an independently confirmed efficiency of 18.4%. Although the device deserves further optimization, the result shows the compatibility of processing on glass with efficiencies exceeding 18%, which opens the door to a high-efficiency solar cell process where the potentially thin wafer is attached to a foreign carrier during the full processing sequence.

Quantum-confined silicon material has been a very active field of research in the years 1990–2000 with the rapid development of opto-electronics. The main application targeted by this research was a light-emitting device (either LED, or laser). In the years 2000–2010, with the emerging need for efficient and cheap photovoltaic devices, new materials, and in particular new silicon-based materials trigger again a special interest. In particular, all-crystalline-Si tandem solar cells where the high-bandgap material is provided by the 2D confinement of excitons in nm-sized nanowires could provide the high-efficiency potential of a tandem device, while taking benefit of the decade-long buildup of knowhow of crystalline silicon material technology (both science and processing). In a first part of this review, we summarize the features described in the relevant literature for the functioning of a photovoltaic device based on Si NWs. This literature shows that from the conceptual point of view such an all-crystalline-Si-tandem solar cell using quantum confined nanowires should be feasible to produce in order to achieve the goal of inexpensive high efficiency (>30%) Si-based solar cells. Keeping the fabrication of efficient photovoltaic devices as driving theme, we review the dense literature of Si nanowires. The literature on the fabrication of nanometer-sized Si nanowires is reviewed in the second part.

In this work three-dimensional (3-D) numerical simulations, validated by the experimental measurements of a reference cell, have been performed to optimize the rear contact geometry of a PERC-type solar cell, featuring a high sheet resistance (140Ω/sq) phosphorus-doped emitter and a front-side metallization with narrow and highly-conductive electro-plated copper lines (40μm wide) on lowly resistive Ti contacts. The simulation results show that an optimization of the rear point contact design potentially leads to an efficiency improvement of 0.68%abs compared to the reference cell.

In this work, an extensive characterisation of intrinsic amorphous silicon (a-Si) passivation layers deposited on n- and p-type silicon is reported. Low temperature capacitance-voltage measurements are utilised to enable parameter extraction from the c-Si/a-Si interface and a-Si bulk. Electron spin resonance enables atomic identification of defects present. Results reveal the presence of electrically active defects at the c-Si/intrinsic a-Si interface (∼1x1012cm-2), and throughout the amorphous silicon layer bulk (∼8x1016cm-3), which are atomically identified as Pb0 centres and D centres silicon dangling bond defects, respectively. The value of this work is the atomic identification of these defects in this stack, coupled with their electrical activity. That they can be detected by these techniques demonstrates the power of the methodology used to assess and quantify these defects. Therein lies the significance of this work: a methodology capable of fundamentally optimising amorphous silicon processing from an atomic perspective.

ABSTRACTWe demonstrate the use of a copper‐based metallization scheme for the specific application of thin‐film epitaxial silicon wafer equivalent (EpiWE) solar cells with rear chemical vapor deposition emitter and conventional POCl3 emitter. Thin‐film epitaxial silicon wafer equivalent cells are consisting of high‐quality epitaxial active layer of only 30 µm, beneath which a highly reflective porous silicon multilayer stack is embedded. By combining Cu‐plating metallization and narrow finger lines with an epitaxial cell architecture including the porous silicon reflector, a Jsc exceeding 32 mA/cm2 was achieved. We report on reproducible cell efficiencies of >16% on >70‐cm2 cells with rear epitaxial chemical vapor deposition emitters and Cu contacts. Copyright © 2011 John Wiley & Sons, Ltd.

To support the feasibility of an all-Si tandem solar cell based on quantum confined Si nanowires, we investigate the diameter reduction of nanowires by thermal oxidation. As a starting point, 6 x 6 mm(2) arrays of vertical nanowires with a 90-nm pitch were made by DUV lithography and anisotropic reactive ion etching. These arrays are subsequently oxidized at temperatures ranging from 825 degrees C to 1150 degrees C. The lower temperature oxidation results in retarded oxidation kinetics, as expected. An unexpected gradual necking and undercutting of the nanowires is however observed for all oxidation temperatures. The effect of temperature on the stress buildup is investigated by process simulation and an eventual solution to the necking problem is found in a two-step oxidation process. This process consists of stopping the oxidation before any necking occurs and removing the oxide before further oxidizing the nanowires to obtain the desired core diameter. (C) 2012 The Electrochemical Society. [DOI: 10.1149/2.088203jes] All rights reserved.

Foil creation by lifting off a thin layer of a high quality silicon substrate is one of the promising substitutes for wafer sawing to create substrates thinner than 100 μm. The porous silicon-based layer transfer process is a well known method to obtain high quality foils. Despite a number of convincing lab-based solar cell show-cases, there is no breakthrough of this technology at (semi)-industrial level, because of the poor yield of processing free standing foils. This paper presents a method to fabricate back contacted solar cells based on epitaxial foils avoiding processes on free-standing foils. First, a porous silicon layer is electrochemically etched, acting as a weak sacrificial layer to detach the foil that is epitaxially grown on top of the porous silicon layer. Characterization of the epitaxial foils shows a good crystalline quality and an effective lifetime around 100 μs. Those results give indications that the obtained foils are well suited for solar cell fabrication. Front-side processing is done while the epitaxial foil is still attached to its parent substrate. A good yield is obtained for epitaxial foils that underwent the front-side processing sequence consisting of wet chemical texturing, FSF formation, passivation and ARC deposition. Afterwards, the front-side of the foil is bonded to a glass carrier and the foil is detached from its parent substrate. Silicone adhesives are used for this permanent bond. The rear-side of the solar cell is processed while bonded to glass. Therefore, only low temperature processes (<;200°C) can be used. So far, the rear-side processing sequence was performed on Float-zone reference wafers as a proof of concept resulting in a confirmed maximum efficiency of 18.4%. The rear-side processing sequence still needs to be applied on epitaxial foils.

Low temperature electron spin resonance studies have been carried out on single crystalline arrays of sub-10 nm Si nanowires (NWs) manufactured on (100)Si by top down etching and oxidation thinning. This reveals the presence of a substantial inherent density of Pb0 (Si3 ≡ Si•) defects (traps) at the NW Si/SiO2 interfaces, due to particular faceting and enhanced interface strain, leaving NW interfaces of reduced electrical quality. Perusal of the specific properties of the occurring Pb-type defect system points to a nanopillar morphology compatible with NWs predominantly bordered by {110} facets, with cross sectional shape of 〈100〉 truncated {110} squares. The inherent interface quality appears limited by the wire-narrowing thermal oxidation procedure.

In this paper, we present the integration of an absorbing photonic crystal within a thin film photovoltaic solar cell. Optical simulations performed on a complete solar cell revealed that patterning the epitaxial crystalline silicon active layer as a 1D and 2D photonic crystal enabled to increase its integrated absorption by 37%(abs) and 68%(abs) between 300 nm and 1100 nm, compared to a similar but unpatterned stack. In order to fabricate such promising cells, a specific fabrication processes based on holographic lithography, inductively coupled plasma etching and reactive ion etching has been developed and implemented to obtain ultrathin patterned solar cells.