This paper presents a high-yielding backside power delivery (BPD) technology, PowerVia, implemented on Intel 4 finFET process. PowerVia more directly integrates power delivery to the transistor as compared to published buried power rail schemes, enabling additional wiring resources on front side for signal routing. A fabricated E-core with $\gt 90$% cell utilization showed $\gt 30$% platform voltage droop improvement and 6% frequency benefit compared to a similar design without PowerVia. Transistor performance, reliability, and fault isolation capability is detailed.

The source-drain punch-through current in off-state TDDB stress (OSS) is shown to significantly affect off-state breakdown behavior. This paper compares various OSS methodologies available in the literature and discusses how source-to-drain punch-through affects off-state breakdown and reliability. The proposed Drain-stress with Offset (DSO) OSS methodology limits punch-through to better reflect the actual field dependence of OSS breakdown for scaled tri-gate MOSFET technologies.

The source-drain punch-through current in off-state TDDB stress (OSS) is shown to significantly affect off-state breakdown behavior. This paper introduces a modified methodology for conducting OSS in scaled tri-gate devices at accelerated conditions that avoids artifacts associated with punch-through while enabling reliability risk assessment. The methodology is validated for both NMOS & PMOS devices and provides consistent degradation mechanism. Finally, it is shown that on-state gate-oxide TDDB remains the reliability limiter compared to OSS TDDB.

FinFET with contact over active-gate (COAG) is implemented on 12nm node technology platform to optimize the Maximum Oscillation Frequency (F MAX ) and the Minimum Noise Figure (NF MIN ) for devices with large fin numbers. This study shows that proposed COAG design can reduce the gate resistance of the 40-fin device by ~10-fold, while improving the F MAX by ~180% with comparable reliability performance to traditional FinFETs. Excellent DC and RF performances with NF MIN of 0.6dB at 26GHz and 3dB improvement in NF with 50Ω source impedance (NF 50 ) over the 5-26GHz frequency range makes large fin number COAG FinFET an excellent candidate for variety of 5G sub-6GHz and mmWave applications in which high F MAX and low noise are critical.

This work presents various device self-heating temperature sensing techniques and discusses their application in device reliability projection. Details of sensor design, technology choice, layout and ambient temperature impact on measurement results are discussed. The sensors produce excellent results which were confirmed through TCAD thermal simulation. Self-heating was studied by varying the number of fins per active region and proximity of sensor to heater was investigated. While most data presented here is on FinFET technology the learning and measurement techniques are applicable to planar technologies. Front-end-of-line (FEOL) reliability mechanism, hot carrier injection (HCI) was studied to show that self-heating effects can impact measurement results and recommendations are given on how to mitigate them. Self-heating is also studied for logic circuits by utilizing ring oscillators with several densities and stage counts to show that self-heating is considerably lower compared to constant voltage stress conditions conducted on discrete structures.

The effect on device reliability mechanisms due to gate metal work function (mWF) in thin and thick gate oxide FinFETs is shown here. Lower BTI is noticed for increasing WFM1 thickness for thin oxide nFETs while higher degradation is seen for thin and thick oxide pFETs. For HCI, the degradation does not correlate and is seen to be independent of WFM1 thickness. For TDDB, t63% increases with increasing V T caused by modulation in WFM1 thickness. A dual trend is noticed in relationship with gate oxide leakage for pFETs for BTI and TDDB. A physical model is proposed which explains the observed reliability behavior.

A multiple workfunction (multi-WF) integration technology was developed for ultra-low voltage operation in high performance FinFETs. It is essential to solve three key issues in the multi-WF process, a) short channel effect (SCE) degradation due to removing halo implants b) gate resistance increase due to multi-WF stack, and c) gate dielectric reliability degradation due to additional patterning. In this study, we resolve these issues through the combination of junction engineering and workfunction metal (WFM) boolean engineering in long channel (LC) and short channel (SC) devices for SCE, WFM stack optimization for gate resistance, and HK interface optimization for reliability. In logic devices, 15/13% N/PFET DC and 14% AC performance were improved without SCE or reliability degradation. In SRAM devices, 43% Vt mismatch (Vtmm) improvement resulted in record Vmin yield down to 0.4V on 128Mb 0.064μm 2 SRAM array.

We proposed a new, simpler, and fully BEOL CMOS-compatible TiN/HfO2/TiN RRAM stack using the Plasma Enhanced Atomic Layer Deposition (PEALD) for the top-electrode TiN processing, demonstrating attractive bipolar switching properties (by positive RESET voltage to the PEALD TiN) in a functional size down to 2275 nm2 (35 nm × 65 nm). Stable switching was observed between a High-Resistive State HRS (∼1 MΩ) and a Low-Resistive State LRS (∼100 kΩ), using a low program current of ∼1 μA. Two different LRS states can be obtained depending on the current compliance (CC) during SET switching, either 100 μA (high-CC LRS) or 10 μA (low-CC LRS), resulting, respectively in LRS resistances of 10 kΩ or 100 kΩ. The projected retention stability of low-CC LRS is ⩾10 years at 80 °C, which is the retention minimum of the TiN/HfO2/TiN RRAM stack. The temperature-dependent resistance showed a non-metallic behavior for the low-CC LRS state (∼100 kΩ), suggesting gentle filament formation.

Introduction: Series resistance (Rseries) is a crucial factor for technology optimization and benchmarking [1-3]. Rseries is typically extracted in the bias conditions where Rseries dominates, i.e., linear regime and high Vgs by comparing multiple gate lengths. However this simple extraction is very challenging for sub22nm CMOS devices as changing a device length / width may change mobility or Rseries. For instance, this is the case for SiGe where the built-in stress effect [5,6] increases the channel mobility thus making the standard extraction difficult. The case is even more compelling for the bulk finfet case where the length width and height may not be known with the necessary precision and the gate stack itself may introduce (un)wanted stress components. As any Rseries extraction do rely critically on assumptions, in this paper we will first test the applicability and limits of several Rseries extraction techniques [1-3] and then use the best of both to gain new insights on the finfet and SiGe technology.

In this work, an extensive characterisation of intrinsic amorphous silicon (a-Si) passivation layers deposited on n- and p-type silicon is reported. Low temperature capacitance-voltage measurements are utilised to enable parameter extraction from the c-Si/a-Si interface and a-Si bulk. Electron spin resonance enables atomic identification of defects present. Results reveal the presence of electrically active defects at the c-Si/intrinsic a-Si interface (∼1x1012cm-2), and throughout the amorphous silicon layer bulk (∼8x1016cm-3), which are atomically identified as Pb0 centres and D centres silicon dangling bond defects, respectively. The value of this work is the atomic identification of these defects in this stack, coupled with their electrical activity. That they can be detected by these techniques demonstrates the power of the methodology used to assess and quantify these defects. Therein lies the significance of this work: a methodology capable of fundamentally optimising amorphous silicon processing from an atomic perspective.

Low-temperature (77 K) capacitance-voltage measurements are proposed as a technique to quantify the densities of traps in c-Si/a-Si:H heterojunction solar cell structures. By comparing the inferred trap densities to the results of electron spin resonance spectroscopy, we found that the dangling bonds of silicon atoms at the surface of the (100)Si substrate (Pb0 centers) and in a-Si:H layer (D-centers) provide the most significant contributions to the density of traps.

A P-SiC (Phosphorus doped Si1-xCx) SD (Source Drain) was developed on bulk-Si based nMOS FinFETs (n-FinFETs). P-SiC epitaxial growth on SD provides strain to boost n-FinFET mobility and drive current. Combination of LA (Laser Anneal) and low temperature RTA recovers P-SiC and PSi (Phosphorus doped Si, Si1-xPx) strain. A SiGe clad channel on pMOS FinFETs (p-FinFETs) was investigated. Narrower Si fin and SiGe epitaxial growth on fins increase mobility and drive current, which is based on the same carrier transport mechanism as conventional phonon scattering without velocity overshoot around 14nm node.

In this work, we present a detailed electrical characterization of TiN\HfO2\Hf\TiN RRAM elements, and show for the first time the intrinsic switching characteristics in the low current operation regime (100uA till few uA's) of small scaled cells (20nm) under DC and fast ramps (up to 1MV/s) condition, using a newly proposed 2R test structure. The main characteristic parameters of the SET and RESET switching are defined and their speed dependence is characterized. Resistance decrease during SET is observed to occur at a constant voltage Vtrans, while symmetrically RESET process starts at -Vtrans. With reducing operation current, mean values of the symmetric SET and RESET transition voltages remain unchanged but their spread strongly increases. The actual I-V characteristics show discrete current jumps and non-linear quantum-mechanical conduction is evidenced and more pronounced at smaller currents. Increasing the ramp rate increases the SET and RESET transition voltage logarithmically with a concomitant reduction of the HRS resistance. These measurements allow for a better insight and understanding of the dynamic switching properties in low-current, ultra-scaled RRAM cells.

An overview is given on the impact of the implementation of high-mobility channel materials and novel device architectures on the low-frequency (LF) noise behavior of 22 nm and below CMOS transistors. It will be shown that a similar 1/f noise power spectral density (PSD) can be achieved for SiGe-channel planar and bulk FinFET devices, whereby mobility fluctuations are dominant. At the same time, it is demonstrated that processing-induced Generation-Recombination (GR) noise can yield a strong device-to-device variability in the PSD. This is illustrated for both bulk FinFETs and thin-film ultra-thin buried oxide (UTBOX) Silicon-On-Insulator (SOI) MOSFETs. A model is presented for the LF noise in narrow, fully-depleted (FD) device structures, allowing the extraction of the oxide trap density profiles and silicon film GR center parameters. This model explains the occurrence of Lorentzian GR noise with gate voltage dependent parameters in planar or vertical FD devices and at the same time points out a new source of noise variability, which becomes important for future bulk FinFET technology nodes.

In this work, (1) we propose a new, simpler, and fully CMOS-compatible TiN\HfO2\TiN material stack, using PEALD TiN which after plasma optimization results in functional cells down to 2275nm(2) (35nmx65nm), (2) we demonstrate stable switching between resistances >10(5)Omega using a low program current of similar to 1 mu A, where the 10(5)Omega-resistive LRS state shows good retention at high temperature, projected to 10 years stability at 80 degrees C.

Physical and electrical characteristics of Metal–Insulator–Metal TiN/HfO2/TiN capacitors have been investigated. A detailed study using internal photoemission and trap assisted transport simulation enabled the extraction of relevant important parameters like barrier height (∼2.5eV) for both injecting interfaces, optical energy gap (∼5.6eV), as well as trap density and energy position within the bandgap (NT=3×1019cm−3; σT=1×10−14cm2; ET=2.0–2.6eV below the bottom of the HfO2 conduction band). The extracted parameters surprisingly showed striking similarities with HfO2 deposited on a Si surface, i.e., in MOSFET process flow. Additionally, Constant Voltage Stress showed a leakage current increase, preferentially at low voltage. This can be explained by preexisting defect precursors (likely related to oxygen vacancies) or by involvement of hydrogen in creating defects as observed on thermal SiO2 layers.

We investigate the roles of TiN and Pt materials used as electrodes in resistive-switching HfO2 systems. Well-behaved reset operation is observed on condition Pt is used as anode, which together with the strong effect of thin insert layers (IL) indicates that the reset switching is favored at the HfO2\Pt interface. However, switching properties are hampered by yield and reliability issues associated to oxygen runaway at forming operation and caused by the Pt permeability to oxygen. TiN\HfO2\(IL)\Pt cells show better reliability due to improved oxygen buffering. The non-polar, unipolar and bipolar switching modes are discussed as originating from similar underlying physical mechanisms. (C) 2011 The Electrochemical Society. [DOI: 10.1149/1.3575165] All rights reserved.