ABSTRACT In this work we announce a ferroelectric charge transfer device that uses a high-k buffer layer underneath the ferroelectric layer as a tunnel oxide, where the high electric field required for Fowler-Nordheim charge tunneling through the buffer layer is provided by the polarized ferroelectric. This device exhibits data retention of 10 years at room temperature while retaining the properties of fast write and low voltage operation. Since the electric field across a buffer layer due to the ferroelectric polarization surface charge is ∼E = P r /ϵ0 ϵ ox then with Pr on the order of 10 μ C/cm2 and ϵ ox for a high k dielectric is ∼20, we have an electric field of 5.6 MV/cm which is sufficient to generate significant tunnel currents across a high–k buffer layer. Charges tunneling from the Si substrate are trapped in the interface between the high-k buffer and the ferroelectric and only detrap thermally; this leads to the long data retention observed on these devices. Despite the fact that charge transfer is accomplished by tunneling, a relatively slow process, this device can be programmed or erased in only the time it takes to switch the ferroelectric, which is of the order of nanoseconds.

YMnO3 thin films were studied on Pt/Ti/SiO2/Si as a candidate for ferroelectric transistor random access memory (FeTRAM). The films were deposited by flash-evaporated metalorganic chemical vapor deposition (MOCVD) at low temperature and post annealed to crystallize the films to form a c-axis oriented hexagonal phase. Polarization versus electric field measurements on metal/ferroelectric/metal capacitors shows a remnant polarization of about 2 μC/cm2 and a coercive field of approximately10 kV/cm. Fatigue stress cycling shows no degradation of films up to 1011 cycles.

To eliminate the interface reaction problems between ferroelectric and semiconductor in MFS (metal-ferroelectric-semiconductor) as well as ferroelectric and insulator in MFIS (metal-ferroelectric-insulator-semiconductor) structures, a gate layer sandwich of the MFMIS (metal-ferroelectric-metal-insulator-semiconductor) is proposed. This structure consists of Pt-SBT-Pt-ZrO 2 -SiO 2 -Si stacks. In the MFMIS structure the MIS capacitor is separated from the ferroelectric MFM capacitor through a metal as a floating gate. Therefore, the MIS capacitor with SiO 2 and ZrO 2 as an insulator with excellent interface properties can be used and MFM acts as an ideal ferroelectric capacitor. As MFMIS is a series combination of MFM and MIS capacitors, it behaves as a voltage divider. The gate voltage is divided according to the capacitance ratio of the MIS and MFM structures. Since the fabricated devices have access to the floating gate, characteristics of the MFM and MIS capacitors can be determined independently to compare the characteristics of the MFMIS structure as a single capacitor. The ferroelectric can be programmed in one direction and the field effect due to that can be analyzed. The MFMIS structures showed significant memory window due to the polarization of ferroelectric thin films but the retention time was short. The short retention time was due to the depolarization field being larger than coercive field of the ferroelectric thin film.

Yttrium manganate (YMO) thin films were prepared on SiO2 buffered silicon as a candidate for ferroelectric transistor random access memory (FeTRAM). The films were deposited by flash evaporated MOCVD at low temperature and post annealed to crystallize the c-axis oriented hexagonal YMO phase. It is found that oxygen content and substrate temperature are major parameters determining c-axis orientation. For the electrical characteristics, P-r (remnant polarization) similar to2 muC/cm(2) and epsilon (dielectric constant) similar to20 are obtained in Pt/YMO/Pt structures. It is also found that a top buffer layer of 30 nm ZrO2 helps to reduce the leakage current of Pt/top buffer/YMO/SiO2/Si stack to 10(-7) A/cm(2) and improves the C-V memory window from 0.2 V to 2 V.