This article describes a defect-oriented test (DOT) approach, which enables a complete physical defect-based automatic test pattern generation (ATPG) for the digital logic area of CMOS-based designs. Total critical area (TCA)-based methods are presented for the generation of needed DOT views to enable the generation of complete DOT-based patterns for detecting all cell-internal and as well all cell-external physical defects. The major aim of these new methods and patterns is to further reduce the defect rate of manufactured ICs, in addition to what is already achieved with traditional and cell-aware test (CAT) fault models. We present test results, including achieved defect rate reduction in defective parts per million (DPPM), from a large 14-nm FinFET design, including a correlation to system-level-test (SLT) fails. For a second, mature 160-nm automotive mixed-signal sensor we present high-volume production test results, again measured in DPPM, and we provide test coverage figures moving away from counting detected faults to calculating detected TCA which is reported as the chip level TCA coverage.

This paper presents new methods and experimental production test results from completely moving away from traditional fault methods towards using critical area based methods instead. The focus of this paper is on measuring the quality of test patterns not by measuring the test coverage but by measuring the covered or detected total critical area (TCA). This is the first time that a TCA for all defects in the digital logic part of a chip can be calculated. The paper will present TCA figures from defect extraction on interconnects outside of standard cells as well as for all defects inside standard cells. We also will present methods for extracting cell-neighborhood defects, their TCA and which of those defects are not covered by cell-aware and interconnect test patterns.

This paper presents DPPM reduction results achieved with new Defect Oriented Test (DOT) methods/patterns applied to designs manufactured in advanced FinFET technologies. Focus of this paper is on Timing-Aware Cell-Aware Test (TA-CAT) patterns targeting small-delay defects of FinFET transistors, and a new DOT method which explicitly targets chip layout dependent cell-neighborhood defects. Test results from traditional Stuck-at/Transition patterns, from traditional CAT patterns, from TA-CAT patterns, and as well from cell-neighborhood patterns, applied to FinFET technology designs, will be presented in this paper. In addition, a correlation to System-Level-Test fails will be discussed.

Stringent quality requirements in the automotive sector result in the necessity of targeting additional fault models beyond traditional stuck-at and transition. This paper is concerned with bridging faults, which are well known to require additional tests to detect those which are not detected by traditional tests. To keep ATPG tractable, bridging faults must be extracted from layout to obtain nodes which are physically close together. There are well established methods for such extraction but typically involve complex flows with several tools. This paper describes a much simpler approach using the same layout database that is used for layout-aware diagnosis. The extraction process automatically ranks bridges on critical area so it is simple to truncate the fault list, if necessary. Since each bridge has a critical area it is also possible to provide a weighted critical area based coverage, which is physically more realistic than a simple fault count. The paper describes experimental results, including coverage gains, critical area calculation, and explores physical versus traditional coverage metrics.

Volume diagnosis of scan fails is au effective method of identifying dominant defect mechanisms for yield improvement. However, traditional diagnosis is at the library cell level and identifies only interconnect defects and defective cells. In practice, many defects affect only the internal logic of cells, such as polysilicon contacts, but cannot be pinpointed, resulting in not identifying some potential yield limiters. This paper describes a solution to the problem by showing how diagnosis can be extended to internal cell defects. This is enabled by characterizing a cell library similar to what is needed for cell-aware ATPG, but including more information for diagnosis such as layout data. A flow is described to produce the characterization, which includes requirements for the cell views. Diagnosis results include layout marker files for cell internal suspects which can be viewed in a GDS newer and used to obtain X/Y coordinates to guide physical failure analysis. Successful implementation is demonstrated for a 160nm automotive product.

Test points are known to improve the fault coverage in BIST applications. This article discusses a new class of test points used to improve the ATPG pattern count in designs that employ embedded deterministic test.

The introduction of FinFET technology has accelerated the adoption of patterns that target cell internal defects such as cell-aware tests. Even though cell-aware tests can replace stuck-at and transition patterns from the screening point of view, we have to address the increase in test data volume. This combined with the growing gate counts enabled by new technology nodes is driving the need for even greater compression levels. In this paper, we present a novel test points technology designed to reduce deterministic pattern counts for cell-aware tests. The technology is based on identification and resolution of conflicts across internal signals allowing ATPG to significantly increase the number of faults targeted by a single pattern. Experimental results on a number of industrial designs with test compression demonstrate that the proposed test points are effective in achieving, on average, a 3×–4× multiplicative increase in compression for 1-cycle and 2-cycle cell-aware patterns.

The semiconductor industry is encountering an increasing number of front-end-of-line defects in the advanced FinFET technology nodes due to extremely small feature size and complex manufacturing processes required for FinFET transistors. Traditional delay diagnosis algorithm has a limited support for cell internal timing related failures based on transition delay faults, and tends to provide a large suspect list. It cannot provide the precise defect location inside the cell that is necessary for effective physical failure analysis and statistical yield learning. In this work, we present a new cell-aware delay diagnosis algorithm, based on accurate delay fault models derived by analog simulation, which can pinpoint the defect location within a cell for various timing related cell internal defects. Preliminary results for real silicon failures show that significant diagnosis resolution improvement can be achieved by the proposed method.

This paper describes the new cell-aware test (CAT) approach, which enables a transistor-level and defect-based ATPG on full CMOS-based designs to significantly reduce the defect rate of manufactured ICs, including FinFET technologies. We present results from a defect-oriented CAT fault model generation for 1,940 standard library cells, as well as the application of CAT to several industrial designs. We present high volume production test results from a 32 nm notebook processor and from a 350 nm automotive design, including the achieved defect rate reduction in defective-parts-per-million. We also present CAT diagnosis and physical failure analysis results from one failing part and give an outlook for using the functionality for quickly ramping up the yield in advanced technology nodes.

The industry is encountering an increasing number of front-end-of-line defects in the most advanced technology nodes due to extremely small feature size and complex manufacturing processes. Traditional scan diagnosis algorithms can locate a defective cell by examining its excitation conditions for cell internal defects, but cannot provide the more precise defect location inside the cell that is necessary for effective physical failure analysis and statistical yield learning. In this work, we propose a new cell-aware diagnosis algorithm, based on accurate fault models derived by analog simulation, that can pinpoint the defect location within a cell for various cell internal defects. The proposed method already has achieved dramatic resolution improvement for real silicon failures.

High quality is an absolute necessity for automotive designs. This paper describes an approach to improve the overall defect coverage for CMOS-based high quality automotive designs. We present results from a cell-aware (CA) characterization flow for 216 cells, the pattern generation flow for a 130nm smart power design, and high-volume production test results achieved after testing multimillion parts. The idea behind CA tests is to detect cell-internal (CI) bridges, opens, leaking and high resistive transistor defects which are undetected with state-of-the-art tests. The production test results have shown that the CA tests detect various failing parts during a first wafer sort test which still resulted into unique failing parts after a second wafer sort test done at a different temperature and with additional tests. The obtained results encouraged us to continue this work beyond this paper to run further experiments with the final goal to eliminate the stuck-at (SA) and transition delay (TR) test by simultaneously improving the quality with CA tests which are a superset of SA and TR tests.

Numerous new multi-conditional fault models have been proposed in the last years. In combination with the increasing complexity of today's designs these new fault models cause a tremendous increases of the ATPG-runtime. In this paper we present a novel fault collapsing scheme for multi-conditional faults. The objective is to significantly reduce the fault set and hence reduce runtime for ATPG and fault diagnosis. The collapsing technique consists of three individual collapsing stages, which are individually discussed and evaluated. Additionally we provide an extensive set of experimental results including runtimes of a state-of-the-art ATPG-tool applied on a set of large industrial designs. We will demonstrate that the achieved reduction of up to 48% of the number of faults also reduces the ATPG runtime significantly.

This paper focuses on an industrial application of the proposed 1687 standard to significantly improve the test development effort and quality of test patterns for mixed signal IPs of an automotive design. The P1687 standard will enable the industry to develop test patterns for IPs on the IP level without having to know how the IP will be embedded within different designs. To measure the impact of P1687, we are applying a commercial P1687 EDA tool on an industrial 65nm automotive design. The presented results underline the significant advantages of P1687 over the current IEEE Std 1149.1-based test methodology, in both, automation of test pattern development as well as reduction of test setup data volume by more than 50%.

Abstract This paper describes a new approach for quickly ramping up the yield for new CMOS technologies by performing a cell-internal (CI) diagnosis based on the cell-aware (CA) methodology. We present results from carrying out this new method on a test chip of a 28-nm technology. After creating defect-oriented CA test patterns for this test chip, we tested various wafers with those CA patterns, selected fail data, conducted a normal electrical failure analysis, and used the new CI diagnosis method to guide the physical failure analysis (PFA) process to look specifically for hot-spot areas within standard library cells. This new approach can reduce the yield ramp-up time significantly.

This paper describes an approach to improve the overall defect coverage for a CMOS-based automotive design. We present results from a defect-oriented cellaware (CA) library characterization and patterngeneration flow and its application to 216 library cells and a high quality automotive design processed in a 350nm technology. The CA flow enabled us to detect cell-internal bridges and opens that caused static, gross-delay, and small-delay defects. We present highvolume production test results achieved after testing 500,000 parts. We also present evaluation results from cell-aware only failing parts.