The stress test of integrated circuits is becoming a significant factor in their production cycle in all application domains. This paper presents a methodology which can be used to quantify the actual stress coverage of Time-Dependent Dielectric Breakdown (TDDB) in arbitrary designs with standard logic cells in an Electronic Design Automation (EDA) flow. The methodology also provides an estimate of overstress or understress. The concept is based on the cell-aware transistor-state stress model (TSSM) that exploits the activity and switching of transistors in the standard cells with an N-detect approach. The experimental results are illustrated on productive designs in deep submicron technologies.

As the industry advances towards smaller geometries for integrated circuits (ICs), internal cell defects have become increasingly crucial to address. Cell-Aware Testing (CAT) has emerged as the industry standard for achieving the high-quality levels required in modern ICs, as it explicitly targets intra-cell defects. However, the comprehensive defect coverage provided by CAT can result in a high test pattern count, which directly impacts test time and production costs.This paper proposes two complementary methodologies to optimize the cell library characterization phase by leveraging weak detections to maximize the number of Don’t Cares (DCs) and equivalent defects. The proposal produces an optimized Defect Detection Matrix (DDM) for the library, which is then used by the ATPG for pattern generation at the design level.The methodologies have been validated by running CAT ATPG for five different designs, using a 65nm cell library characterized with the proposed approach. The experimental results show that using the optimized DDMs reduces the number of patterns by an average of 8% and the pattern generation time by 11%, depending on the methodology used and the circuit analyzed.

Physical Unclonable Functions (PUFs) are integral for generating unique signatures, secret keys, and device identification, leveraging inherent manufacturing process variability. Mathematically defined as functions linking inputs (challenges) to outputs (responses), PUFs exhibit random properties. Key properties for high-quality PUFs include intra-device entropy (random distribution of responses within the same circuit), inter-device entropy (random distribution across different circuits for identical challenges), and reliability (response consistency for identical challenges and the same circuit). Inter-device entropy and reliability may be influenced by design discrepancies, systematic variability, noise, and aging. This paper addresses the correlation between entropy and reliability, providing evidence from an extensive set of circuits featuring diverse Ring Oscillators supplied by Infineon.

Performance screening is an essential test for modern automotive microcontrollers (MCUs). Such a test determines the maximum achievable frequency F MAX of the MCU. On-chip ring oscillators (ROs) are used as indirect monitors for performance screening. The performance is determined by using the RO frequencies. This work uses various ROs to train a classification-based machine learning model that does a pass/fail classification based on a preset threshold value. An accuracy of over 97 % is achieved. The proposed performance screening flow selects the most appropriate subset of ROs and extracts sharp test limits that are directly applicable to the productive test flow.

LBIST has been proven to be an effective measure for reaching functional safety goals for automotive microcontrollers. Due to a large variety of recent innovative features, every customer can adjust LBIST settings in a way that fits their use case. The downside of these user-defined configurations is the handling of their golden signatures: Traditionally, they can be computed only with access to the gate-level netlist. This is typically not possible for MCU customers because a netlist contains protected IP, which cannot be disclosed to third parties.This paper proposes a digital twin of the LBIST functionality that can overcome this drawback. It is an executable model that can be delivered together with the product. As a result, for the first time, a customer can compute a golden signature without knowledge of the netlist or other support of the supplier. We prove the efficacy of the digital twin in an industrial environment on an automotive microcontroller.

The testing of integrated circuits is an important topic, particularly in safety-critical applications. This is especially true for microcontrollers (MCUs) used in the automotive industry. A critical test is the performance screening in which the maximum clock frequency of the MCU is determined. For this performance screening, indirect monitors, such as ring oscillators (ROs), are used. This article presents a holistic overview of the functional path RO from the pre-silicon to the post-silicon. The implementation of such ROs is presented, as the associated advantages in terms of area consumption, leakage, and routing. In the post-silicon phase, the functional path RO frequencies are correlated with the MCU performance using machine learning approaches.

Automotive Microcontrollers (MCUs) are extensively tested to guarantee zero-defect quality. Performance screening is one of the critical factors to ensure that MCUs meet quality requirements. Ring Oscillator (RO) structures are used for this performance screening. Such RO structures usually cause routing overhead on the chip. The routing overhead increases, especially when many ROs are implemented. This paper presents a novel self-enabling technique that significantly reduces the routing overhead for functional path ROs. We present a proof of concept on a large automotive MCU. The routing overhead can be reduced by over 80% compared to traditional approaches.

A lot of effort and money is invested in testing to ensure zero-defect quality of automotive microcontrollers. One crucial test is the performance screening. Indirect structures such as Ring Oscillators (ROs) are used for this. Here, the quality of the performance screening strongly depends on the quality and selection of the RO structures used. This paper proposes a path selection and implementation method to provide a set of functional path ROs with good representativeness for the whole chip. In addition, a simulation-based validation is presented, which is used to improve the selection process continually. The proposed path selection is validated by simulation and on silicon. The results show a high diversity and good coverage of the chip parameters with the selected functional path ROs, providing good conditions for a high-quality performance screening.

The automotive industry sets high reliability standards for microcontroller (MCUs). To increase reliability, the automotive MCU manufacturers are looking for accurate performance screening. One of these performance screening mechanisms are functional path ring oscillators (RO). In this paper, a scalable and efficient method for creating functional path ring oscillators is presented. Implementation data demonstrate that functional path RO monitors show a significant advantage in area and power consumption over comparable performance screening methods.

As cars become increasingly computerized and their safety functions evolve rapidly, the number of complex safety-critical components deployed in advanced driver assistance systems or autonomous vehicles is rising dramatically with high-end models containing hundreds of embedded microcontrollers. These integrated circuits must adhere to stringent requirements for high quality and long-term reliability driven by functional safety standards. This requires test solutions that address challenges posed by automotive systems. This article presents a scan-based test scheme optimizing test time and area overhead during manufacturing and in-system test of automotive electronics. The proposed scheme deploys observation test points that capture the faulty effects in every shift cycle into separate observation scan chains. To reduce area overhead, the scheme enables the sharing of flip-flops among control points. It is also shown how test points enhance test coverage (TC) in the presence of cascaded clock gaters. Finally, processing challenges when fault simulating every scan shift cycle to determine TC are addressed. Experimental results obtained for contemporary automotive designs and reported herein show significant improvements in test quality over traditional solutions.

This work presents a novel hybrid compression architecture that seamlessly combines the advantages of an embedded test compression technique with a lightweight codeword-based compression scheme. Embedded test compression has proven to be beneficial and is widely used in industrial circuit designs. However, particularly, in test applications within low-pin-count environments, a certain number of test patterns is incompressible and will, therefore, be rejected. This leads to a test coverage decrease which, in turn, jeopardizes the zero defect policy of safety-critical applications like automotive microcontrollers. Therefore, the rejected test patterns are typically transferred in an uncompressed way bypassing the embedded compression, which is extremely costly. The proposed hybrid architecture mitigates the adverse impact of rejected test patterns on the compression ratio as well as on the test application time of state-of-the-art techniques. The experimental evaluation of industrial-sized designs clearly shows that a significant compression ratio up to 67.4% and a test application time reduction up to 72.9% can be achieved when utilizing the existing multi-channel interfaces.

This work presents a novel hybrid compression architecture that seamlessly combines the advantages of an embedded test compression technique with a lightweight codeword-based compression scheme. The proposed architecture tackles the shortcomings of state-of-the-art techniques, which are widely to address the rising challenges of safety-critical applications enforcing a zero defect policy. Embedded test compression techniques had been introduced that allow the compression of a large share of the test patterns. However, depending on the test application (e.g. low pin count test) there is a certain number of test patterns, which are incompressible due to the architecture and will be rejected. This leads to a test coverage decrease which, in turn, jeopardizes the zero defect policy. Therefore, the rejected test patterns are typically transferred in an uncompressed way bypassing the embedded compression, which is extremely costly. The proposed hybrid architecture mitigates the adverse impact of rejected test patterns on the compression ratio as well as on the test application time of state-of-the-art techniques. The experimental evaluation of industrial-sized designs clearly shows that a significant compression ratio up to 67.4 % and a test application time reduction up to 65.7% can be achieved.

As cars become increasingly computerized and their safety functions are evolving rapidly, the number of complex safety-critical components deployed in advanced driver assistance systems or autonomous vehicles is progressively rising with high-end models containing more than a hundred embedded microcontrollers. These integrated circuits must adhere to stringent requirements for high quality and long-term reliability driven by functional safety standards. This requires test solutions that address challenges posed by automotive electronics. The paper presents a scan-based LBIST scheme optimizing test time and area overhead during in-system test applications for automotive ICs. It ensures highly reliable operations of ICs for the duration of their lifespan. The proposed scheme works with observation test points that capture faulty effects every shift cycle into separate observation scan chains. To reduce area overhead, the scheme takes advantage of a procedure allowing one to share flip-flops among control points. It is also shown how test points can enhance test coverage in the presence of cascaded clock gaters. Finally, processing challenges when fault simulating every scan shift cycle to determine observed faults are addressed. Experimental results obtained for contemporary automotive designs and reported herein show significant improvements in quality of test over traditional BIST schemes.

The 1-Pin Test concept has proven to be beneficial for test cost reduction. By compacting test responses into a signature and reading them out at test end, test parallelism can be increased significantly. This reduces the test time and thus test cost. Especially cost-sensitive devices, e.g. IoT end nodes, profit. A drawback of this method is the limited capability of diagnosis due to the lack of cycle-accurate PASS/FAIL information. In this paper, we present a new approach to tackle this challenge. It enables the use of an industrial diagnosis flow for fails that occurred during 1-Pin Test. For this purpose, we propose failing vector and failing cycle analysis techniques. Our approach is fault model independent and not limited to a single fault assumption. We mitigate the aliasing problem by masking. The effectiveness of our approach is shown on an investigation of real silicon fails in industrial designs.

The emerging Internet-of-Things (IoT) paradigm creates a new market for very small and cost-sensitive chips. Design costs must be as low as possible in order to be competitive. In this context, the 1-pin test has proven to be a beneficial way to significantly reduce test costs. However, the incorporated signature generation requires an X-free design, which is not always possible (e.g. due to timing exceptions in transition tests). Available X-masking approaches target large circuits and are therefore not suitable due to their large area overhead or because they require additional pins. In this paper, we present a solution to this business case problem. A new X-masking scheme with very small area overhead and the ability for usage during 1-pin test is proposed. We present experimental results on industrial designs. Those experiments show for the first time that transition tests with X-values in their response can be applied during 1-pin test. The method has been successfully verified on silicon and is already being applied during productive test application.

Launch-Switching-Activity (LSA) is a serious problem during at-speed testing of integrated circuits, since localized LSA may lead to severe IR-drop and thus failures. The excessive LSA is conventionally mitigated by reducing the switching activity through special low-power test generation techniques, typically resulting in severe test pattern inflation and high test costs. This work introduces a novel concept of Low-Capture-Power Test Points (LCP-TPs), which are inserted to reduce switching activity in critical High-Capture-Power (HCP) regions. LCP-TPs also help in retaining high test compaction capability. An optimization- SAT based procedure is proposed to compute a small set of optimal LCP-TP locations for compact at-speed test sets with effective capture power reduction. Experimental results clearly demonstrate the advantages of LCP-TP insertion.

X values may be captured by scan flipflops during the scan test. An X value corrupts the signature generated by a Multiple-Input Signature Register (MISR). The MISR is used in the test structures such as Logic Built-in Self-Test (LBIST). In this paper, we propose an approach to automate formal verification of X propagation with respect to testability issues. The propagation of an X value from X sources to scan flipflops is comprehensively evaluated using formal verification considering all possible test patterns. The approach is utilized to find root causes of a corrupted signature generated by MISR and to rectify the erroneous behavior of a design because of dangerous X sources.

It was shown in the past that ATPG based on the Boolean Satisfiability problem is a beneficial complement to traditional ATPG techniques. Its advantages can be observed especially on large industrial circuits. These circuits usually contain a lot of functional redundancy which, on the one hand, is often needed during operational mode, but on the other hand, causes dispensable overhead during ATPG. Using the traditional circuit-to-CNF transformation, this redundancy is also contained in the SAT instances. The contribution of this paper is a new technique to improve the SAT instance generation for SAT-based ATPG. The objective of the proposed method is to use Binary Decision Diagrams (BDDs) to optimize the resulting CNF representations. In order to apply the proposed technique to industrial circuits, we developed dedicated BDD operations using a multiple-valued logic. The experimental results, obtained on large industrial designs, show that the accomplished optimizations result in a considerable acceleration of the overall ATPG runtime as well as in a significant reduction of the unclassified faults.