In this work, we demonstrate advances in plasma dry etch technology applied to common materials in semi-additive fineline processing for panel-level packaging. Emphasis is placed on deep reactive-ion etching into organic dielectric build-up materials as a scalable process for making vertical interconnects (vias). A capacitively coupled dual frequency plasma module was used for our experiments. We investigate the influence of different process parameters and gas mixtures on via shape, via sidewall quality and residue formation. To enable material-selective etching, a metallic hard mask is used, patterned by direct imaging lithography. For the removal of the hard mask we introduce a non-etching lift-off approach. Furthermore, a dry etch removal of sputtered Ti barrier and Cu seed layers is shown.

Fan-out Wafer and Panel Level Packaging are two of the dominating trends in microelectronics packaging. Both approaches with different flavors as RDL last face-up or face- down have reached maturity and are introduced in high volume manufacturing. For Fan-out Wafer Level Packaging (FOWLP) clear application trends and technology roadmaps do exist. These range from low density core technology for e.g. RF or PMIC (power management IC) packaging over high density application processor packaging to ultra-high-density applications for networking servers etc.. For panel level packaging it is still not fully clear if the same performance can be achieved as on wafer level as larger process / panel sizes may have higher challenges in process control, accuracy and consistency, material and equipment or handling.Main driver for moving to panel level packaging is of course lowering the packaging cost. More packages can be processed in parallel and panel formats have a much better area utilization (ratio between panel/wafer size and package size) than round wafer shapes. Also, environmentally PLP is advantageous by e.g. lower waste and smaller carbon footprint. However, for both aspects processes with sufficiently high yield are required. This is especially true for FOWLP/PLP RDL last processes as a failure in the RDL will also lead to a loss of packaged die(s).This paper describes current technology developments to access the limits of the panel level packaging technology. Warpage, die shift and fine line capabilities are the main topics here. To better understand the compression molding process as the technological basis of the reconfigured panel and its influence on warpage and die shift a dedicated sensor mold tool has been developed. By integration of temperature, pressure, dielectric and fiber Bragg grating sensors the flowing and curing behavior of epoxy molding compound can be studied in-situ. Results will support process simulations for warpage prediction and more accurate die shift compensation.For large panel processing an adaptive patterning approach might be needed anyhow to achieve a high yield. Here the combination of an intelligent assembly strategy for high speed and sufficient accuracy, capabilities to measure each die position and a maskless lithography process adapting the redistribution layer (RDL) to each die position may lead to a cost-effective high yield process.In addition, a clear trend towards finer lines and spaces as well as smaller via diameters is also demanded for large panel RDL processes. Process developments towards 2 μm lines and spaces and via shrinking on 610x457 mm 2 (24"x18") panels are shown including material and process options.In summary this paper will show current PLP technology developments for future high-end applications and will cover at the same time economic and environmental aspects.

The ongoing miniaturization and functional heterogeneity in electronics packaging are pushing the demand for advanced substrate technologies. Highly integrated, advanced multi-chip packaging solutions combine application, logic and computing dies with memory or components for power management in a single package. A solution to achieve low fabrication costs is the close embedding of thin dies in IC Substrates based on large formats (600 x 600 mm²), known from PCB fabrication. In a consortium of partners from industry and research advanced technologies for Panel Level Packaging (PLP) are developed. This paper will show the development of 5µm L/S RDL routing density and chips with 50µm bump pitch. Here, the 6x6 mm² dies are symmetrically embedded into an organic laminate matrix. A PCB core (100µm thickness) with very low coefficient of thermal expansion (CTE) containing laser cut cavities is used, acting as a frame layer. Besides mechanical and handling stability, the usage of such a frame offers the advantage of pre-integrating additional features like local fiducials, through vias or power lines by conventional PCB processes. Within that frame, the dies are embedded by lamination of an organic build-up film with 25µm thickness equal to bump height. The chip contacts are then opened without the need of any micro via formation. Here a strong focus is set on RIE etching of the polymer material. Highly accurate measurement of the real die position is essential for the following processing. The formation of the redistribution layer (RDL) is done in a semi-additive process (SAP) utilizing sputtering technique and direct imaging (LDI). To achieve the fine pitch demands, an adaptive imaging process is applied. Therefore, a newly developed LDI machine is used to write structures in a 7µm photoresist. This exposure also combines the measurement data of the real die position and the adaption of the exposure artwork, in order to achieve highest registration quality.

Within the advanced packaging technologies there is an increasing demand for very high I/O count solutions to fulfill requirements of high performance computing applications like big data analysis. Thus, the density of lateral and vertical interconnects is being pushed to its limits to achieve a minimum delay in communication between chips or chiplets from different technology nodes. Here we focus on dry etch technology as an approach to overcome the difficulties of currently used processes for the formation of vertical interconnects (vias) in organic buildup films. Nowadays, laser drilling into the organic dielectric is the state-of-the-art technology to prepare vertical interconnects between the Cu layers. However, drawbacks like sequential processing, limited control of sidewall smoothness or registration accuracy become extremely challenging when millions of sub-vias have to be realized on 600 mm2 panels. One alternative technique to address the need of forming steep microstructures in various materials is deep reactive-ion etching (DRIE). In this paper we analyze how DRIE could be applied for via formation in silica-filled organic dielectric build-up films. Our approach included a metallic hard mask for material-selective etching and for generating various via diameters. For our experiments, a dual frequency capacitive coupled plasma (CCP) tool was used. The plasma etch module was designed for panel-level substrates up to size and was integrated into a high volume manufacturing system. We investigated the influence of different gas mixtures, power settings on etch rate, selectivity (e.g. on silica and organic), directionality, uniformity and homogeneity. The overall compatibility and implications of the dry etching approach for the semi-additive process and redistribution layer formation have been discussed.

Advanced packaging technologies like wafer-level fan-out and 3-D system-in-package (3-D SIP) are rapidly penetrating the market of electronic components. For cost reduction, one approach is the migration of processes from wafer to panel format, called panel-level packaging (PLP). In a consortium of partners from industry and research, advanced technologies for PLP are developed. The project aims for an integrated process flow for 3-D SIPs with chips embedded into an organic laminate matrix. At first, 6 mm $\times 6$ mm chips (100 $\mu \text{m}$ thickness) with Cu bumps (25- $\mu \text{m}$ height, 110- $\mu \text{m}$ pitch) are placed into cavities of a printed circuit board (PCB) core layer. They are embedded by vacuum lamination of thin organic films. The core is equipped with fiducials for local alignment and provides handling robustness. Developments aim for a final panel size of 600 mm $\times600$ mm (here 227 mm $\times305$ mm demonstrated). Onto the contact side of embedded chips, a 25- $\mu \text{m}$ dielectric film is applied. The copper bumps are subsequently opened by plasma etching. By sputtering and electroplating of Cu, electrical contacts to the chips are formed without via opening. High-aspect-ratio vias as an element for vertical interconnects are formed by UV laser drilling. At via diameters of 17 $\mu \text{m}$ , a drill hole depth of 74 $\mu \text{m}$ was achieved (aspect ratio 4.4:1). Using a newly developed electrolyte, microvia filling was achieved for aspect ratios up to 4:1. With a newly developed direct imaging (DI) machine, 4- $\mu \text{m}$ structures in a 7- $\mu \text{m}$ dry film photoresist are formed. Adaptive imaging of a redistribution layer was realized.

The ongoing roadmaps of miniaturization and functional heterogenity in electronics packaging are pushing the demand for advanced substrate technologies. In this paper we show the embedding in core cavity (EiCC) process running with 5 μm L/S and chips with 50 μm bump pitch. Two 6x6 mm2 dies are symmetrically embedded into an organic laminate matrix. A PCB core (100 μm thickness) with very low coefficient of thermal expansion (CTE) containing laser-cut cavities acts as a frame layer. Besides mechanical and handling stability the usage of such a frame offers the advantage of pre-integrating additional features like local fiducials, through vias or power lines by conventional PCB processes. Within that frame the dies are embedded by lamination of an organic build-up film. The chip contacts are then revealed in process based on plasma etching. After measuring chip positions the first redistribution layer (RDL) is formed in a semi-additive process (SAP) utilizing sputtering technique and adaptive laser direct imaging (LDI). Therefore, a newly developed LDI machine is used to write structures in a 7 μm photoresist. Subsequently a second RDL formation can be done. In this step high aspect ratio blind microvias with 20 μm diameter and up to 80 μm depth are drilled by UV-laser and filled in the following plating process. Altogether, with the combination of high density 5 μm L/S interconnects, high aspect ratio (2.5:1) blind microvias and 50 μm fine bump pitch on large panel formats we will give an outlook to upcoming challenges and possibilities in FO PLP.

Highly integrated, advanced multi-chip packaging solutéons combine application, logic and computing dies with memory or components for power management in a single package. A solution to achieve low fabrication costs is the close embedding of thin dies in IC Substrates based on large formats (600 × 600 mm 2 ), known from PCB fabrication. In rr consortium of partners from industry and research advanced technologies for Panel Level Packaging (PLP) are developed. Here, dies are symmetrically embedded under law stress into pre-manufactured IC substrates. The Embedding in Cores with Cavities (EiCC) targets towards low cost and thin packages (<; 150 pm) with multiple, heterogeneous components. The biggest disadvantage is the potentially low yield due to low assembly accuracy and process tolerances during the embedding process. This paper presents recent results to optimize the yield of the EiCC process chain. We assemble two 6×6 mm, 100 pm thin dies with 25 pm high Cu pillars face down on a temporary adhesive foil with two assembly concepts, varying assembly throughput and accuracy. After embedding the stack in Ajinomoto Build-Up Film (ABF), laser drilled vias and u semi-additive Process (SAP) with 10 μm lines and space with a copper thickness of 5 pm acts as electrical routing between the daisy chain structured dies. Based on practical work we compare the known status of precision focussed manufacturing against a rule-based system that acquires data with a Coordinate Measurement Machine (CMM), rearranges fabrication plans and forwards data along the process chain.

Advanced packaging technologies like wafer-level fan-out and 3D System-in-Package (3D SIP) are rapidly penetrating the market of electronic components. A recent trend to reduce cost is the extension of processes to large manufacturing formats, called Panel Level Packaging (PLP). In a consortium of German partners from industry and research advanced technologies for PLP are developed. The project aims for an integrated process flow for 3D SIPs with chips embedded into an organic laminate matrix. At first 6x6 mm 2 chips with Cu bumps (100 μm pitch) are placed into holes of a PCB core layer with low coefficient of thermal expansion (CTE). They are embedded by vacuum lamination of thin organic films, filling the small gap down to 15 μm between chips and core. The core provides fiducials for a local alignment of following processes, limits die shift during embedding and gives a remarkable handling robustness. Developments are initially performed on a 305x256 mm 2 panel format, aiming for a final size of 600x600 mm 2 . On the top side of embedded chips a 25 μm dielectric film is applied and the bump surface is exposed by plasma etching. By sputtering and electroplating of Cu contacts to the chips are formed without via opening. High aspect ratio vias around the chip to lower interconnect layers are formed by UV laser drilling. At via diameters of 17 μm a drill hole depth of 74 μm was achieved (aspect ration 4.4:1). Currently a microvia filling by Cu plating using a newly developed electrolyte could be demonstrated for aspect ratios up to 2.5:1. Then in a 7 μm dry film photo resist forming of 4 μm RDL structures was demonstrated by a newly developed Laser Direct Imaging (LDI) machine.

Advanced packaging technologies like wafer-level fan-out and 3D System-in-Packages (SIPs) are rapidly penetrating the market of electronic components [1]. A recent trend to reduce cost is the extension of processes to large manufacturing formats, called Panel Level Packaging (PLP). In a consortium of German partners from industry and research advanced technologies for PLP are developed. The project aims for an integrated process flow for SIPs with chips embedded into an organic laminate matrix. At first dies with Cu pad metallization with 100μm contact pitch are placed into openings of a laminate frame layer with very low coefficient of thermal expansion (CTE). They are embedded by vacuum lamination of thin organic films, filling the very small gap down to 15μm between chips and frame. The frame provides alignment marks for a local registration of following processes. The ridged frame limits die shift during embedding and gives a remarkable handling robustness. Developments are initially performed on a 303x227mm² panel format, aiming for a final size of 610x615mm². On the top side of the embedded chips, a 20μm dielectric film is applied. Micro via to the chip contacts as well as high aspect ratio blind vias around the chip to lower interconnect layers are formed by UV laser drilling. The formation of fine, high aspect ratio, laser drilled vias is an essential technology step. Another way would be an approach which avoids drilled via connections and realizes a direct contact to the RDL lines. Conventional metallization sequences, like thin copper foils as base and electroless or direct copper metallization of vias, are not suitable for high density routing demands. That’s why as the following step TiW/Cu or Ti/Cu barrier and seed layer is applied by sputtering. Subsequently high resolution photoresist is applied and exposed by a newly developed Direct Imaging (DI) system. Lines and spaces of 4μm were already achieved. In the following, Cu is simultaneously electroplated for via contacts and interconnects traces. Finally, the photo resist is stripped and the TiW or Ti barrier and Cu seed layers are etched. The paper will discuss the new developments in detail, with the focus of a new developed technology sequence.

CuI is a p-type transparent conductive semiconductor with unique optoelectronic properties, including wide band gap (3.1 eV), high hole mobility (>40 cm2 V−1 s−1 in bulk) and large room-temperature exciton binding energy (62 meV). The difficulty in epitaxy of CuI is the main obstacle for its application in advanced solid-state electronic devices. Herein, room-temperature heteroepitaxial growth of CuI on various substrates with well-defined in-plane epitaxial relations is realized by reactive sputtering technique. In such heteroepitaxial growth the formation of rotation domains is observed and hereby systematically investigated in accordance with existing theoretical study of domain-epitaxy. The controllable epitaxy of CuI thin films allows for the combination of p-type CuI with suitable n-type semiconductors with the purpose to fabricate epitaxial thin film heterojunctions. Such heterostructures have superior properties to structures without or with weakly ordered in-plane orientation. The obtained epitaxial thin film heterojunction of p-CuI(111)/n-ZnO(00.1) exhibits a high rectification up to 2 × 109 (±2 V), a 100-fold improvement compared to diodes with disordered interfaces. Also a low saturation current density down to 5 × 10−9 Acm−2 is formed. These results prove the great potential of epitaxial CuI as a promising p-type optoelectronic material.

We present the history of, and the latest progress in, the field of bipolar oxide thin film devices. As such we consider primarily pn-junctions in which at least one of the materials is a metal oxide semiconductor. A wide range of n-type and p-type oxides has been explored for the formation of such bipolar diodes. Since most oxide semiconductors are unipolar, challenges and opportunities exist with regard to the formation of heterojunction diodes and band lineups. Recently, various approaches have led to devices with high rectification, namely p-type ZnCo2O4 and NiO on n-type ZnO and amorphous zinc-tin-oxide. Subsequent bipolar devices and applications such as photodetectors, solar cells, junction field-effect transistors and integrated circuits like inverters and ring oscillators are discussed. The tremendous progress shows that bipolar oxide electronics has evolved from the exploration of various materials and heterostructures to the demonstration of functioning integrated circuits. Therefore a viable, facile and high performance technology is ready for further exploitation and performance optimization.

The electrical properties of identically fabricated PtOx Schottky contacts on ((2) over bar 01)-oriented gallium oxide thin films and bulk crystals were investigated using current-voltage measurements at room temperature. The homogeneous barrier height of the Schottky contacts on thin films is 1.55 +/- 0.15 eV, which is significantly smaller than that of those fabricated on bulk single crystals, 2.01 +/- 0.12 eV. This large difference indicates an upward band bending of 0.4-0.5 eV at the surface of the bulk crystals in the as-received state, which is explained by the larger net doping density of the thin films compared to the single crystals. (C) 2015 The Japan Society of Applied Physics

Fully amorphous pn-heterodiodes consisting of n-type zinc-tin oxide and p-type zinc-cobalt oxide are discussed. All fabrication steps are conducted at room-temperature except two baking steps within the photolithography for 90 s at 90 degrees C. Rectifications as high as six orders of magnitude are achieved and the ideality factors are between 1.2 and 2, depending on the diode design.

We present integrated inverter circuits based on junction FETs (JFETs) with ZnO channels and amorphous ZnCo2O4 gate contacts. The inverters reach high gain values up to 276 and uncertainty ranges down to 0.3 V for an operating voltage of 3 V. The magnitude of the gain is traced back theoretically to the slope of the JFET saturation current. The use of a level shifter is demonstrated, in order to obtain full inverters, which can be integrated into logic circuits.

We report on advances in the fabrication of high quality bipolar heterodiodes with oxideelectrodes. The highest rectification above 10 10 is obtained for a structure from a-ZCO/ZnO/ZnO:Alon Al 2 O 3 (a-ZCO: amorphous ZnCo 2 O 4 ). Rectification better than 10 6 , a value larger than reportedfor all previous attempts, is obtained for our a-ZCO/a-ZTO (a-ZTO: amorphous zinc tin oxide), a-NiO/ZnO and CuI/ZnO diodes. The ZCO/ZnO has been used as gate in JFETs with ZnO as channel.The bipolar diodes open the field of oxide semiconductor electronics to applications in photovoltaics.

We present oxide bipolar heterojunction diodes consisting of p-type ZnCo2O4 and n-type ZnO fabricated by pulsed-laser deposition. Hole conduction of ZnCo2O4 (ZCO) was evaluated by Hall and Seebeck effect as well as scanning capacitance spectroscopy. Both, ZCO/ZnO and ZnO/ZCO type heterostructures, showed diode characteristics. For amorphous ZCO deposited at room temperature on epitaxial ZnO/Al2O3 thin films, we achieved current rectification ratios up to 2 x 10(10), ideality factors around 2, and long-term stability. (C) 2014 AIP Publishing LLC.

We compare key properties of zinc oxide (ZnO)-based junction field-effect transistors (JFETs), metal-semiconductor field-effect transistors (MESFETs), and metal-insulator-semiconductor field-effect transistors (MISFETs) prepared from a common ZnO:Mg thin film. The JFETs are fabricated with a ZnCo 2 O 4 -gate, the MESFETs with reactively sputtered Pt-gate and the MISFETs with WO 3 as gate insulator. The three FET types are compared with regarding dc characteristics, frequency dependence, and stability at temperatures up to 150°C. All devices can be switched within a similar gate voltage range of less than 3 V, making a direct comparison of the device characteristics possible. Measurements above room temperature show a common shift of the transfer curves to higher gate voltages, which seems to be a distinguishing property of ZnO compared with other semiconductors. All electric measurements show major differences between the devices, which can be attributed to the different gate structures.

Halide semiconductors stand at the very beginning of semiconductor science and technology. CuI was reported as the first transparent conductor, and the first field effect transistor was made from KBr. Although halogens are frequently used in semiconductor preparation, little use is currently made from halide semiconductors in electronics and photonics. We review past reports on the metal halide semiconductor CuI and related alloys and discuss recent progress with regard to this material including its use in organic electronics and solar cells as well as our own work on fully transparent bipolar heterostructure diodes (p-CuI/n-ZnO) with high rectification of several 10(7) and ideality factors down to 1.5.[GRAPHICS]gamma-CuI(111) thin film on glass (1x1cm(2)) and IV-characteristics of p-CuI/n-ZnO/a-Al2O3 bipolar heterojunction diode. (C) 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim

Transparent and electrically conducting p-type copper(I)-iodide thin-films form highly rectifying p-CuI/n-ZnO diodes. Sputtered copper thin films on glass were transformed into polycrystalline γ-CuI by exposing them to iodine vapor. The electrical parameters extracted from Hall effect are p=5×1018 cm−3, μh,Hall=6 cm2/Vs, and ρ=0.2 Ωcm for hole concentration, mobility, and electrical resistivity, respectively. Heterostructures consisting of p-CuI and pulsed-laser deposited n-ZnO were fabricated on a-plane sapphire substrates. The p-CuI/n-ZnO diode exhibits a current rectification ratio of 6×106 at ±2 V and an ideality factor of η=2.14.

ZnO-based junction field-effect transistors were fabricated by pulsed-laser deposition using room-temperature-deposited amorphous p-type ZnCo 2 O 4 as heterojunction gate on top of a n-ZnO channel layer. A channel mobility of 8.4 cm 2 /(Vs), current on/off ratio of 1.3 ×10 7 , and a subthreshold swing of 91 mV/dec were achieved for a transistor with a 40 nm thin channel layer. The devices are normally on and show excellent bias-stress stability, exhibiting a negligible threshold-voltage shift. Elevated temperatures up to 150 ° C changed the device performance slightly, but the transistor remains fully operative.