III-V technology provides improved the RF performances in term of output power compared with standard CMOS technology. However, their integration into a system is challenging due to their thin top level contact made out of gold. Because of that, standard bumping cannot be applied. This paper presents the embedding PCB-based technology from Fraunhofer IZM which can embed the III-V active components (in this case from GaN technology) in different 5G/6G mm-wave frequency bands (39 GHz and 170 GHz). This technology enables the integration of antennas within the module, utilizing the Antenna in Package (AiP) topology. This integration reduces the overall size of the system, providing a compact solution.

Today’s power electronics modules typically consist of a ceramics substrate (DBC – Direct Bond Copper), carrying IGBTs, diodes or MOSFETs. These semiconductors are soldered or sintered to the ceramics and their top sides are interconnected by thick Al wires. An integration of further components or functions on the DBC substrate is difficult or even not possible. Therefore, driver circuits and controllers have to be mounted to a separate substrate, typically an organic Printed Circuit board (PCB). The PCB has to be connected to the DBC by wires or pins. The mechanical integration of the whole system requires a bulky housing. Embedding of power semiconductors like SiC MOSFET allows a significant size reduction, improved electrical performance and a high degree of reliability of such modules. In the last years, the capability of PCB embedding technology for the realization of low and high voltage power modules was demonstrated. Fraunhofer IZM together with partners from the industry demonstrated the feasibility for different applications, from single die SiC packages to high voltage automotive traction inverters. In this paper, a general overview about innovative power module technologies will be given and the embedding of power semiconductors will be introduced in detail. It will address all most relevant point, like the demands on the semiconductor, the thermal and electrical considerations as well as the demands on the used materials. To address the integration of the required driver circuits and controllers, the idea of modularization such electronics systems will also be presented. Here already packaged components will be used and embedded into PCB layers too. As a result, a modular approach to form a complete system will be developed. Different functional layers, e.g. power switches, logic modules, will be formed and finally stacked und connected to form the system. The concept and first realized demonstrators will be discussed.

Along with the large scale implementation of 5G networks a number of crucial technical challenges are still under development. Some of these are concerning the packaging and module developments, where the implementation of a large number of signal connections compatible with high data rates, the use of novel RF materials and finally new process approaches are the main issues to be tackled. Within the European funded project SERENA, an integration platform based on printed circuit board (PCB) embedding technology was developed. The technology enables the reduction of module size, system power consumption, design time, and complexity. At the same time improved performance and transmitted output power were achieved. In particular, by PCB embedding integrated RF electronic modules containing ICs for RF signal generation in very close proximity to the antennas were realized in a single package, thus minimizing the signal path losses. In the framework of the project, new materials suitable for the embedding of RF-components are used in combination with high gain GaN and SiGe dies. In this way a scalable System-in-Package operating at 39 GHz was ultimately implemented. In the course of the project a low and a high power module have been investigated. A functional low power module was fabricated at Fraunhofer IZM. Two process technologies had to be adopted (1) a combination of novel RF laminate and high-end prepreg materials to embed the dies into the build-up of the PCB and (2) the electrical connection of 3 µm Au contact pads by laser drilling and electroplating. Electrical test structures were fabricated in parallel to assess the electrical performance of package configuration and technology. Package interconnects and integrated patch antenna arrays were designed based on simulations with a 3D full-wave EM simulator (AnsysEM HFSS). The simulated structures were fabricated and measured using a network analyzer. The very short interconnection signal path between the passive and active elements realized in the PCB embedding technology achieve very low insertion (less than 0.4 dB) and return loss (better than 20 dB).The antennas in the package designed and fabricated using the PCB embedding technology achieved a wide bandwidth (3.1 GHz) with a peak gain of 8.8 dBi. Mutual coupling less than - 20 dB is obtained over the entire frequency range of interest between the elements of the antenna, thus making it suitable for beamforming. The approach proved to be well suited for the fabrication of 5G System-in-Package RF modules. The paper will give a detailed description of the fabrication processes and will discuss the technological approaches in depth. A brief overview of the electrical results will be given.

Autonomous robots for survey and control tasks are increasingly used in environments which can not or not easily be explored by humans. The autonomy of such platforms is based on representation or mappings of the local environment into which the robot is immersed. Advanced autonomous systems in natural environments typically record, evaluate and finally use a multitude of sensor data, e.g. for navigation or sample retrieval. Depending on the type of parameter a single sensor may be sufficient, but more often arrays of the same sensor type are distributed over the robot in order to provide the necessary data. As an example of a distributed sensor network we describe in the present paper the skin of an autonomous underwater vehicle. The vehicle is inspired by a manta ray: size and locomotion are the bionic copy of a ray. The skin of the vehicle is a textile which is permeable for water and spanned over the internal skeleton of the vehicle. The aim of the project “Roboskin” is to equip that skin with an array of sensor nodes to detect touch, nine axis-orientation, and pressure. The touch sensors, three on each wing, form the human machine interfaces [HMI] for the control of the vehicle by a diver. Orientation sensors are used for the self-representation of the robot movement and pressure sensors do monitor pressure distribution inside the vehicle while moving. Additional large area coils around the circumference of both wings are used for the detection of metals, which are related to the use case of the robot. The skin is equipped with a four wire bus structure stitched onto the skin of the robot. Two wires are for data (controller area network (CAN)-bus) and two for energy transmission. Touch sensors and metal detectors are likewise realized by stitching respective coils onto the skin. At defined positions “sensor housings” are joined up in the bus structure by plug connectors and mechanically fixed to the skin. They contain a connector structure for the miniaturized sensor nodes which are mounted into the housing and subsequently encapsulated with a lid. In order to realize as small as possible and highly robust sensor nodes, the electronic build up was realized using embedding technology of components into a printed circuit board. This allows the highest possible miniaturization of a heterogeneous system (i.e. non-monolithic), a high flexibility for design/fabrication modifications and an optimized protection of the electronic components. The resulting sensor node can easily be integrated into the housing, which is finally flooded with a protective grease to prevent water do diffuse into the electronics. The system specification of the device requires high density routing in a four layer printed circuit board build-up. Layer interconnects therein are a mixture of µ-vias and plated through holes. A single embedded layer contains more than 20 passive components with various package types and a number of active components like µ-controller, orientation sensors, and CAN-transceivers. All components are soldered onto the core prior to embedding into the printed circuit board by lamination. The embedded components were positioned with smallest possible spacing and are thus packed very densely. A particular challenge therefore is the configuration of the prepreg stack around the components, having different heights depending on component type, prior to the embedding. After lamination through holes and blind vias are drilled and plated, followed by photolithographic structuring of the copper. Finally onto the top side of the embedded module the pressure sensor is mounted as a single component on the outside of the embedded module. The yield of a typical fabrication run of the embedded sensor nodes is after ramp up above 90 %. Summarized this paper shows the potential of embedding technology towards maximum miniaturization and high robustness for a highly challenging application. Design rules for highest integration are provided and a brief description of target application including sensor data gained is given.

The technology to embed electrical components into build-up layers of printed circuit boards has considerably evolved during the past 20 years. Although the basic concept has been first described already in 1969, only 30 years later serious developments took place some of which have now reached full industrial maturity. At present there is not only a single embedding technology, but different approaches are used to embed components. Bare die embedding is nowadays industrialized and used as a packaging technology for a variety of different products. On the other hand, the embedding of surface mount devices into the build-up of the printed circuit board allows a high degree of miniaturization and improved robustness of more complex electronic systems. Although the principle is rather simple, it is far from being an established technology in a typical printed circuit board house. The focus of this presentation will be on the design, the types of components and processes for the surface mount devices embedding. The results of a representative variety of projects, which have been conducted at Fraunhofer IZM and TU Berlin during the past five years will be presented. In these projects highly integrated multi-component packages were fabricated in flexible and yet robust manner. It ranges from energy autonomous sensor node to record environmental data, which are transmitted wireless into an IoT data cloud. This module is equipped with a helix antenna, holds replaceable battery, and for the environmental data acquisition is equipped with a sensor that has an ambient access. Another example is an encapsulated sensor and control node integrated into the surface of an autonomous under water vehicle. In this module a single embedded layers contains about twenty passive components in various package types and a variety of active components like u-controller, orientation sensors, and CAN-transceivers (power and data transmission). As a third example an approach for embedded modules with a hermetic sealing which are used in harsh environments will be presented. The sealing of such modules realized by the integration of a ceramic platelet with electrical feedthroughs on top surface of the module, while all other surfaces of the module are fully covered with plated Cu. The ceramic platelet is connected to the wiring structure of the embedded build-up. Since the packing density of the embedded surface mount devices is typically very high, a tight and void-free encapsulation of the components with epoxy resin is critical during embedding process. In order to determine the appropriate prepreg stack for the build-up, detailed tests with respect to resin filling and the adhesion of resin and the surface mount devices were carried out. In some cases, surface treatments (wet cleaning, plasma, laser roughening) were used to improve the interface integrity. After initial fabrication runs to adjust process parameters and conduct first functional tests, typical production yields are in the range of 95 percent and higher, depending on the complexity of the embedded system.

Technologies and building blocks for the realization of reliable electronic systems for the use in harsh environments are attracting increasing intention. Harsh environments are for instance high temperature, pressure, mechanical stress and/or submerge into corrosive liquids, or the combination thereof. In the first place electronic components like integrated circuits or passive components which constitute the electronic system need to be operational under harsh conditions. On system level also the interconnections and package materials need to withstand the loading conditions. Printed circuit board embedding technology is a highly promising approach to realize this kind of electronic systems. Embedded semiconductors and passive components are mechanically protected from the environmental stresses by the epoxy/glass fibre compound into which they are encapsulated. Furthermore, novel types of high temperature laminate materials are commercially available since a few years. In an electroless plating process a fully hermetic metallic encapsulation can be added to the modules. This encapsulation acts as a protective barrier when they are immersed into corrosive liquids or gases. The external electrical connections out of the package are realized by ceramics with metallic feed throughs. They are assembled onto the modules (prior to the metallic encapsulation) using sinter-lamination-technology, i.e. the simultaneous build-up lamination and a sintering process. Two application demonstrators were realized in order to show the general viability of the encapsulation process. All used materials are commercially available. Industrial process equipment was used throughout the manufacturing. Subsequent reliability tests provide evidence for the general robustness and functionality of the modules under harsh environmental conditions. This work was part of the Fraunhofer lighthouse project “eHarsh” which was funded by the Fraunhofer Society.

Power electronic systems equipped with wide band gap semiconductors like SiC and GaN are attracting increasing attention due to the superior functionality of these materials. Especially for automotive, aerospace and energy grid applications a large market potential is expected, which is reflected in massive investments in respective semiconductor development and fabrication. In order to make full use of the semiconductor properties, however, not only the single components but the whole system has to be taken into account. Major aims in system optimization is the reduction of dc voltage link inductance, optimization of heat dissipation and an overall miniaturization and robustness of modules. Thus, the shortening of interconnect length, the integration of thermal dissipation structures and a compact three-dimensional build-up of systems are at the core of ongoing developments in power electronics. During the past decade, embedding of electronic components into printed circuit board has proven to be a highly promising technology for large-scale fabrication that can meet these requirements. In this paper we present a fabrication approach that is applicable in any printed circuit board fabrication, since only standard equipment is used. As basic building blocks, pre-packaged power semiconductors were used. The fabrication of these will be described briefly. Power components of this type are now commercially available from some suppliers. For the module fabrication, first a typical insulated metal substrate is fabricated. Onto the copper structures, sinter paste is printed to mount pre-packages and vertical resistors. A prepreg-layup is then assembled which surrounds the components. The final layer of the stack is a two-layer power core for electrical routing, which is equipped with sinter depots for top side connection of the components. The stack is laminated with an initial pressure and temperature overshoot in order to facilitate the sintering process. Subsequently the profile resumes conventional parameters in order to cure the prepreg and finalize the lamination process. Surface mounted ceramic capacitors soldered to the top complete the low-impedance dc-link buffer circuit. Damping resistors were embedded into the PCB module, which besides compactness enables an excellent cooling of the module. This technology pushes the fast-switching SiC and GaN power semiconductors to the next step. The drastic reduced switching overvoltage of only 4%, demonstrated for 950 V operation, enables a significantly improved utilization of the semiconductors.

Metasurfaces (MSs) have been utilized to manipulate different properties of electromagnetic waves. By combining local control over the wave amplitude, phase, and polarization into a single tunable structure, a multi-functional and reconfigurable metasurface can be realized, capable of full control over incident radiation. Here, we experimentally validate a multi-functional metasurface architecture for the microwave regime, where in principle variable loads are connected behind the backplane to reconfigurably shape the complex surface impedance. As a proof-of-concept step, we fabricate several metasurface instances with static loads in different configura-tions (surface mount capacitors and resistors of different values in different connection topologies) to validate the approach and showcase the different achievable functionalities. Specifically, we show perfect absorption for oblique incidence (both polarizations), broadband linear polarization conversion, and beam splitting, demon-strating control over the amplitude, polarization state, and wavefront, respectively. Measurements are performed in the 4-18 GHz range inside an anechoic chamber and show good agreement with theoretically-anticipated results. Our results clearly demonstrate the practical potential of the proposed architecture for reconfigurable electromagnetic wave manipulation.

In this paper, a double stacked microvia (DSV) in a novel Antenna-in-Package (AiP) system integration platform (SiP) is investigated for 5G millimetre-Wave (mmWave) applications. To demonstrate the performance of the DSV as a vertical interconnect element in printed circuit board (PCB) based AiP, DSV along with conductor-backed co-planar waveguide (CB-CPW) were modelled to achieve optimum performance. The designed structures were fabricated and measured. Very good correlation was obtained between measurement and simulation. The fabricated DSV along with CB-CPW has an insertion loss of less than 0.3 dB up to 40 GHz.

This paper brings into light all the new developmental work performed in the wide domain of high frequency PCBs for the realisation of innovative metasurfaces at 5GHz as well as compact highly integrated 5G antenna-in-modules at 40 GHz. There is a fast growing demand in high frequency market that justifies the intense R&D work also on microwave and especially mmWave technologies, comprising both “beyond the state-of-the-art high frequency PCBs” and advanced PCB integration concepts. In this context, this paper intends to highlight new knowledge in materials, processes as well as thermal dissipation concepts, that have been derived from various R&D projects, but especially in the framework of the FET-EU “Visorsurf” and the EU-Serena projects. In specific, R&D work will be shown on the emerging concepts of metamaterials that can be software programmable and adapt their properties. The Visorsurf main objective is the development of a hardware platform, the Hypersurface, whose electromagnetic behavior can be programmatically defined. The key enablers for this are the metasurfaces whose electromagnetic properties depend on their internal structure. The Hypersurface hardware platform will be a 4-layer build-up of high frequency PCB substrate materials with the metasurfaces on the top and custom electronic controller nodes at the bottom of the PCB hardware platform. This paper will elaborate on how innovative PCB processes have been tailored to high frequency substrates for the manufacturing of the first 4-layer Hypersurface PCB hardware platform with a size of 300mmx300mm.}{In a complimentary way, the paper will describe in detail new chip embedding concepts in the same family of high frequency PCB substrates toward the realization of highly miniaturized advanced packages for 5G mmWave applications at 40 GHz. These concepts show vividly the potential of PCB embedding technologies as the mean for heterogeneous integration in high frequency advanced packages/modules. The paper discusses in detail all process chain developments in high frequency PCBs for the embedding of GaN and SiGe chips in PCBs, their interconnection path concept, the embedding of passives, the fabrication of the antenna module and its stacking on a high power or low power PCB module for the final formation of a 6-layer antenna-in-module package which could be separately assembled on the system board. Furthermore, the paper will present for the first time innovative thermal dissipation concepts for the “Serena” antenna module, with the prevailing scenario of thermal vias to the bottom of the GaN and SiGe chips for direct heat removal. All processes for realization of high frequency substrates and embedded 5G 40 GHz antenna modules will be discussed in detail.

The ongoing miniaturization and functional heterogeneity in electronics packaging are pushing the demand for advanced substrate technologies. Highly integrated, advanced multi-chip packaging solutions combine application, logic and computing dies with memory or components for power management in a single package. A solution to achieve low fabrication costs is the close embedding of thin dies in IC Substrates based on large formats (600 x 600 mm²), known from PCB fabrication. In a consortium of partners from industry and research advanced technologies for Panel Level Packaging (PLP) are developed. This paper will show the development of 5µm L/S RDL routing density and chips with 50µm bump pitch. Here, the 6x6 mm² dies are symmetrically embedded into an organic laminate matrix. A PCB core (100µm thickness) with very low coefficient of thermal expansion (CTE) containing laser cut cavities is used, acting as a frame layer. Besides mechanical and handling stability, the usage of such a frame offers the advantage of pre-integrating additional features like local fiducials, through vias or power lines by conventional PCB processes. Within that frame, the dies are embedded by lamination of an organic build-up film with 25µm thickness equal to bump height. The chip contacts are then opened without the need of any micro via formation. Here a strong focus is set on RIE etching of the polymer material. Highly accurate measurement of the real die position is essential for the following processing. The formation of the redistribution layer (RDL) is done in a semi-additive process (SAP) utilizing sputtering technique and direct imaging (LDI). To achieve the fine pitch demands, an adaptive imaging process is applied. Therefore, a newly developed LDI machine is used to write structures in a 7µm photoresist. This exposure also combines the measurement data of the real die position and the adaption of the exposure artwork, in order to achieve highest registration quality.

In this work, we present a novel packaging and system-integration platform with integrated antennas (antenna-in-package, AiP, platform) for 5G millimeter-wave (mmWave) systems. We illustrate the application of the platform for the development of miniaturized, scalable, low-cost and high-performance 5G mmWave systems for new radio (NR) base stations. RF characterization of the dielectric material of the platform and the integrated mmWave antennas as well as thermal investigations of the platform are presented. The process steps required for the fabrication of the platform are discussed, and an example of a mmWave chip embedded in the platform is shown.

Advanced packaging technologies like wafer-level fan-out and 3-D system-in-package (3-D SIP) are rapidly penetrating the market of electronic components. For cost reduction, one approach is the migration of processes from wafer to panel format, called panel-level packaging (PLP). In a consortium of partners from industry and research, advanced technologies for PLP are developed. The project aims for an integrated process flow for 3-D SIPs with chips embedded into an organic laminate matrix. At first, 6 mm $\times 6$ mm chips (100 $\mu \text{m}$ thickness) with Cu bumps (25- $\mu \text{m}$ height, 110- $\mu \text{m}$ pitch) are placed into cavities of a printed circuit board (PCB) core layer. They are embedded by vacuum lamination of thin organic films. The core is equipped with fiducials for local alignment and provides handling robustness. Developments aim for a final panel size of 600 mm $\times600$ mm (here 227 mm $\times305$ mm demonstrated). Onto the contact side of embedded chips, a 25- $\mu \text{m}$ dielectric film is applied. The copper bumps are subsequently opened by plasma etching. By sputtering and electroplating of Cu, electrical contacts to the chips are formed without via opening. High-aspect-ratio vias as an element for vertical interconnects are formed by UV laser drilling. At via diameters of 17 $\mu \text{m}$ , a drill hole depth of 74 $\mu \text{m}$ was achieved (aspect ratio 4.4:1). Using a newly developed electrolyte, microvia filling was achieved for aspect ratios up to 4:1. With a newly developed direct imaging (DI) machine, 4- $\mu \text{m}$ structures in a 7- $\mu \text{m}$ dry film photoresist are formed. Adaptive imaging of a redistribution layer was realized.

The proposed work is performed in the framework of the FET-EU project "VISORSURF", which has undertaken research activities on the emerging concepts of metamaterials that can be software programmable and adapt their properties. In the realm of electromagnetism (EM), the field of metasurfaces (MSF) has reached significant breakthroughs in correlating the micro- or nano-structure of artificial planar materials to their end properties. MSFs exhibit physical properties not found in nature, such as negative or smaller-than-unity refraction index, allowing for EM cloaking of objects, reflection cancellation from a given surface and EM energy concentration in as-tight-as-possible spaces. The VISORSURF main objective is the development of a hardware platform, the Hypersurface, whose electromagnetic behavior can be defined programmatically. The key enablers for this are the metasurfaces whose electromagnetic properties depend on their internal structure. The Hypersurface hardware platform will be a 4-layer build-up of high frequency PCB substrate materials and will merge the metasurfaces with custom electronic controller nodes at the bottom of the PCB hardware platform. These electronic controllers build a nanonetwork which receives external programmatic commands and alters the metasurface structure, yielding a desired electromagnetic behavior for the Hypersurface platform. This paper will elaborate on how large scale PCB technologies are deployed for the economical manufacturing of the 4-layer Hypersurface PCB hardware platform with a size of 9" × 12", having copper metasurface patches on the top of the board and the electronic controllers as 2mm × 2mm WLCSP chips at 400 μm pitch assembled at the bottom of the platform. The PCB platform designs have stemmed from EM modeling iterations of the whole stack of high frequency laminates taking into account also the electronic features of the controller nodes. The manufacturing processes for the realization of the selected PCB architectures will be discussed in detail.

Emerging applications and markets from Internet of Things to electrical vehicles need power converters with small footprint, low thermal losses and capability for integration into various environments. The expected big market for converters in the arising digital world asks for decreasing cost and more efficient manufacturing processes. New integration technologies allow realization of Power System-in-Packages and power modules with outstanding electrical and thermal performance. These integration technologies comprise embedding of semiconductors in printed circuit board structures as well as the location of passive components in power packages and modules. They enable the realization of flat devices with small footprint, which allows a cost-efficient manufacturing of many parts in parallel on large production formats. Power packages and System-in-Packages are in series production for years already. Automotive 48 V power modules have been announced, while high voltage modules are still being evaluated. This paper discusses the benefits of integration technologies and explains different manufacturing processes. A combination of different integration technologies, embedded semiconductors and passives in the module, will be demonstrated by a direct water cooled device for 850 V and 100 A. It contains four prepacked SiC MOSFETs in a half bridge configuration. A primary DC link capacitor and damping resistor directly on top lead to a DC link inductance of less than 2 nH.

The ongoing miniaturization at different levels seems to be an constant in electronics development. It allows not only to increase in functionality in novel product generations, but also the spreading of electronics into new environments. In recent years, especially the application of electronic functions close to or onto the human skin (i.e. by textiles or band aids), implants and novel biomorphic user interfaces have attracted considerable development efforts. It turns out, however, that miniaturization alone does not cover all requirements in the indicated application fields. Typical systems consist of sensors/actuators, data processing and transmission, and quite often relatively bulky power supplies. In order to meet the mechanical requirements of novel products (softness, drapability), miniaturized system elements are laterally distributed and interconnected by appropriate wiring architectures. A common feature of the above indicated application cases is the conformation of the distributed electronic systems to three-dimensional free form surfaces, which are either dynamically moving (human skin) or static. In order to conform to different types of surfaces the systems typically need to sustain a certain elongation repeatedly (in dynamical applications) or at least once during a forming process. At Fraunhofer IZM a portfolio of technologies, summarized as conformable electronics, has been developed, encompassing textile, stretchable circuit boards, paste printed and thermo-formable electronics on a variety of dielectric carrier materials. Each technology provides on one hand the electrical interconnection network and on the other hand technologies to assemble, interconnect and encapsulate electronic components thereon. Having been developed separately it turned out, that combination of the technologies are possible which leads to a number of synergies and extended of application potentials.

Advanced packaging technologies like wafer-level fan-out and 3D System-in-Packages (SIPs) are rapidly penetrating the market of electronic components. A recent trend to reduce cost is the extension of processes to large manufacturing formats, called Panel Level Packaging (PLP). In a consortium of German partners from industry and research advanced technologies for PLP are developed. The project aims for an integrated process flow for SIPs with chips embedded into an organic laminate matrix. At first dies with Cu pillar structures are placed into openings of a laminate frame layer with very low coefficient of thermal expansion (CTE). They are embedded by vacuum lamination of thin organic films, filling the very small gap down to 15 μm between chips and frame. The frame provides alignment marks for a local registration of following processes. The ridged frame limits die shift during embedding and gives a remarkable handling robustness. Developments are initially performed on a 305×256mm2 panel format, aiming for a final size of 610×615 mm2. On the top side of embedded chips, a 20μm dielectric film is applied. The goal is to avoid additional via formation and to realize a direct connection between the Cu pillar of the die and the RDL The RDL formation is based on semi-additive processing. Therefore a Ti or TiW barrier and Cu seed layer is sputtered. Subsequently a 7μm photoresist is applied and exposed by a newly developed Direct Imaging (DI) system. Lines and spaces of 4μm were achieved with high yield. In the following, Cu is simultaneously electroplated for the via contacts and interconnects traces. Finally, the photo resist is stripped and the TiW barrier and Cu seed layers are etched. The goal of the development is to provide a technology for a high-density RDL formation on large panel sizes. The paper will discuss the new developments in detail, e.g. the influence of most significant process parameters, like lithographical resolution, minimum via diameter and the placement and alignment accuracy on overall process yield.

The ongoing roadmaps of miniaturization and functional heterogenity in electronics packaging are pushing the demand for advanced substrate technologies. In this paper we show the embedding in core cavity (EiCC) process running with 5 μm L/S and chips with 50 μm bump pitch. Two 6x6 mm2 dies are symmetrically embedded into an organic laminate matrix. A PCB core (100 μm thickness) with very low coefficient of thermal expansion (CTE) containing laser-cut cavities acts as a frame layer. Besides mechanical and handling stability the usage of such a frame offers the advantage of pre-integrating additional features like local fiducials, through vias or power lines by conventional PCB processes. Within that frame the dies are embedded by lamination of an organic build-up film. The chip contacts are then revealed in process based on plasma etching. After measuring chip positions the first redistribution layer (RDL) is formed in a semi-additive process (SAP) utilizing sputtering technique and adaptive laser direct imaging (LDI). Therefore, a newly developed LDI machine is used to write structures in a 7 μm photoresist. Subsequently a second RDL formation can be done. In this step high aspect ratio blind microvias with 20 μm diameter and up to 80 μm depth are drilled by UV-laser and filled in the following plating process. Altogether, with the combination of high density 5 μm L/S interconnects, high aspect ratio (2.5:1) blind microvias and 50 μm fine bump pitch on large panel formats we will give an outlook to upcoming challenges and possibilities in FO PLP.

As of today, various solutions to handle the dissipating heat of power electronics devices are available. These include the application of heatsinks, overmolding, embedding of components into substrates, use of substrates with embedded metal or ceramic heatsinks or liquid cooling approaches. When it comes to power electronics for high voltages and fast switching the parasitic capacity has to be considered. This parasitic capacity affects the electrical performance and may finally even lead to damage of the device. Embedding of metal heatsinks or mounting a substrate to a metal heatsink can even increase the parasitic capacity and hence, worsen the scenario. In this project a rectifier had to be built suitable for voltages of up to 20 kV and switching frequencies of 100 kHz while achieving a low parasitic capacity of max. 3 pF. High voltage diodes were selected to meet the electrical requirements. To fullfil both the thermal and capacitance demands the diodes were embedded into a substrate made from a highly thermal conductive FR4 material. In addition, the substrate is mounted to a ceramic heatsink to enable a superior cooling but to limit the parasitic capacity at the same time. This setup was characterised for its thermal management behaviour in the as build state. Though the lamination of the substrate to the ceramic heatsink showed some challenges its cooling performance could be assessed. Subsequently, the system without the ceramic heatsink was exposed to temperature shock cycles at -40/+125°C for up to 2,000 cycles to analyse the long term stability of the system behaviour. For the repeated investigation of the thermal behaviour and the structural integrity of the system a novel analysis approach using an infrared camera was applied. Cross sections were done in addition to verify the results from the novel thermal analysis approach. As of now no thermo-mechanical damage of the rectifier could be observed proving the ability of the embedding approach and the validity of the results gained with the novel non-destructive analysis approach.