A following of diverse degradation indicators during the ageing in operational conditions of AlGaN/GaN HEMTs (high electron mobility transistors) is proposed. Measurements of pulsed I–V, Schottky barrier height, RF output power and gate current versus output power during the early phase of the ageing test (2000 h on a 6000 h total) are presented. These preliminary results give insight on some of the principal degradation indicators that are interesting to follow during an ageing test close to operational conditions on such components.

The reliability of RF AlGaN/GaN HEMT devices on SiC substrate is investigated here in pulsed RF condition at nominal and maximum rating drain quiescent bias. During these 3500hour tests, high voltage especially during the RF pulse leads to a progressive decrease in gm and IDSS while trap concentration increases. These evolutions may be attributed to trap generation by hot carrier injection and highlight the importance of drain quiescent voltage as an important acceleration factor for this technology's reliability in pulsed RF conditions.

This chapter concerns the study of radiofrequency power amplifiers’ reliability, for RAdiowave Detection And Ranging (RADAR) applications, based on gallium nitride transistors. Compared to the literature, this study combines electrical characterization, aging tests and physical analysis. It shows that temperature is the main degradation parameter and the gate contact is a more sensitive transistor element. All analysis tools lead to this conclusion. We also present in this chapter a novel and preliminary electrical model which consists of introducing reliability early in the design phase.

GaN High Electron Mobility Transistors (HEMTs) are very promising for high power switching and radiofrequency operation. However, the lack of reliability feedback is one of its major drawbacks. Trapping effect especially is one of the main performance limitations of such components. Many measurement techniques exist for trapping effects characterization, especially for short time constant traps (μs to several ms). However for longer time constants, self-heating may distort the measurements. This paper presents an electrical and athermal transient measurement method which has been developed to study the trapping and detrapping time constants of such components. It allows the extraction of slow transients without self-heating problems and is usable in long term electrical stress experiments. A simulation of this method with a simplified component's model and the measurements results are presented. With this technique, we investigated especially the long time constants (τ > 20 ms) over a range of temperature from 10 °C to 105 °C. We observed three thermally activated trap signatures on GaN devices with our method.

This chapter describes how to perform power microwave transistors lifetime tests in operational conditions. The originality of this test bench is its ability to monitor automatically component performance during thousands of hours and to apply electrical and thermal stresses. This equipment is used to test high power transistors operating in pulsed mode and to record electrical parameter drifts using in-situ static and dynamic electrical characterization. The results of different aging processes of laterally diffused metal oxide semiconductor (LDMOS) high power transistors are presented

This paper deals with the physical study of the Schottky contact after pulsed-RF saturated life test under enhanced drain bias voltage on power HEMTs. Electrical measurements showed a pinch-off voltage (VP) shift, a decrease of output power and average drain current while Photon Emission Microscopy (PEM) was used to identify the degradation distribution along the 80 fingers die. Finally, Transmission Electron Microscopy (TEM) is performed to point out the different Schottky degradation between a central finger and an outer one.

Reliability knowledge of AlGaN/GaN High Electron Mobility Transistors (HEMT) remains a major challenge to provide safe power devices. In order to understand degradation mechanisms related to this technology, accurate life tests must be performed. In this paper, saturated-pulsed-RF stress tests at enhanced drain bias voltage are performed on an AlGaN/GaN HEMT based power amplifier. These tests have permitted to highlight the device's parameters responsible for the performance drop. Finally, they have been included in a large signal HEMT model to predict the power amplifier behavior under enhanced drain bias voltage operation. Results on a 45V drain bias voltage ageing test and the way to integrate them in a large signal model are discussed. Then, measured and simulated amplifier performances are compared.

AlGaN/GaN HEMTs are on the way to lead the RF-power amplification field according to their outstanding performances. However, due to its relative youth, reliability studies in several types of operating conditions allow to understand mechanisms peculiar to this technology and responsible for the wearing out of devices. This paper reports the reliability study on two power amplifiers using AlGaN/GaN HEMT. Based on results of a previous study of 1280h in standard operating conditions wherein no evolution of electrical parameters have been observed, two ageing tests in deep class-AB (432h) and class-B (795h) are performed under pulsed-RF operating life at high drain bias voltages and saturated operation. This study shows a drift in RF performances which is linked with the evolution of electrical parameters (RDSON, gm and VP). Similar kinetics and amplitude of degradations are observed revealing quasi-similar contribution of thermal effects in both cases. Degradations are supposed to be related to trapped charges phenomena induced by high voltage operating conditions. Although, several results attest to this hypothesis, a part of the evolutions seems to be linked with structural changes.

A study of the classical RLC equivalent passive model for CMOS transistor only simulated inductors (TOSI) is presented. The model is compared with a four branches RLC model and its frequency performances and limitations are discussed. The analysis is applied on a particular active inductor topology for frequencies between 0.45 GHz and 3.3 GHz, the study being focused on the resonant frequency and inductance value. As simulations show, the model accuracy is strongly dependent on transistor parasitics and device modeling. It is shown that the second model is more accurate regarding the inductance value while the classical one is helpful for simplified calculus with respect to the resonant frequency. These considerations are valid in case of using charge based transistor model only. The simulations were carried out in 0.35μm AMS CMOS process.

The gate and bulk resistances influence on the impedance matching in case of MOSFET common gate amplifiers is investigated. It is shown that using a supplementary resistance of maximum 100Ω, S 11 becomes less than -15 dB over a wide frequency range, therefore making the circuit suitable for low power wideband RF applications and less sensitive to the loading capacitor value, at the price of a supplementary noise. The simulations were carried out in 0.35μm AMS CMOS process.

A study of the classical RLC equivalent passive model for CMOS transistor only simulated inductors (TOSI) is presented. The model is compared with a four branches RLC model and its frequency performances and limitations are discussed. The analysis is applied on a particular active inductor topology for frequencies between 0.45 GHz and 3.3 GHz, the study being focused on the resonant frequency and inductance value. As simulations show, the model accuracy is strongly dependent on transistor parasitics and device modeling. It is shown that the second model is more accurate regarding the inductance value while the classical one is helpful for simplified calculus with respect to the resonant frequency. These considerations are valid in case of using charge based transistor model only. The simulations were carried out in 0.35μm AMS CMOS process.

This paper reports the design and measurement of a GaN power amplifier whose output loads are optimised at fundamental and 2nd harmonic over a wide bandwidth (20%) in S-Band to reach maximum power added efficiency (PAE). The design methodology is described in the paper. Two power amplifiers have been built. The first one is optimized at fundamental and 2nd harmonic while the other one is only optimised at fundamental. Comparisons of power measurement results demonstrate the interest of optimising load impedances at the 2nd harmonic over large bandwidths for GaN HEMTs. When loaded by the matching circuit optimised at the 2nd harmonic, the packaged GaN exhibits 23.4Watts (9.7W/mm) output power associated to 15.2dB power gain and 69% PAE at the low frequency of the bandwidth (fmin). The paper also proposes a new matching architecture at 2nd harmonic frequency.

A fully monolithic radio transceiver front-end for wireless applications of 2.4 to 2.5 GHz band is presented in a 0.35 mu m SiGe BiCMOS technology. This high performance transceiver contains a receive (Rx) chain with a two-stage cascode low noise amplifier, an active transversal band-pass filter, an active down-conversion Rx mixer, and a transmit (Tx) chain composed of a Gilbert-Cell based up-conversion Tx mixer, an active band-pass filter and a high-gain Driver Amplifier. A low-size LC-tuned MOS-VCO with a phase noise of -130.3 dBc for 1 MHz offset from center frequency was integrated to drive the mixers. The high linear receiver exhibited a gain of +27 dB and an excellent noise figure (NF) of 3 dB, while the transmit string has a gain of 29.4 dB and an output-referred third-order intercept point (OIP3) of +17.5 dBm. The overall receiver and transmitter consumption is about 170 mW and 180 mW for a 3.3V DC supply, respectively.

This paper describes a monolithic tunable active time delay with variable gain, designed using monolithic-microwave integrated-circuit (MMIC) technology, targeting in 3.5-4.5 GHz range with a low power consumption of 9.4 mW. It is impossible to realize such great delays with ideal transmission line in MMIC, because of the length required for the line. In this paper We present analytical and computer-simulated results using 0.35 mum SiGe BiCMOS process for a tunable active time delay in 3.5-4.5 GHz range. It works as a pure time delay over 800 MHz frequency band.

This paper describes a low voltage low noise amplifier (LNA), designed using 0.35 mu m SiGe BiCMOS process, targeting a center frequency of 5.8GHz with a voltage supply 1.2V. A power gain of 12.1dB at 5.8GHz has been achieved with a low power consumption of 3.8mW, including all biasing circuitry. The overall noise figure of the LNA is 3dB with both input and output impedance matched to 500.

Fully differential voltage-controlled oscillator (VCO) design with a low phase noise and extra linear VCO gain (Kvco) for 5-GHz wireless applications in 0.35-mu m SiGe (Silicon Germanium) BiCMOS technology is discussed in this paper. The phase noise level is -120.976 dBc/Hz at 1MHz offset at an oscillation frequency of 5.4 GHz The Kvco changes from 214 MHz/V to 271 MHz/V. The tunability of the structure covers 786 MHz, from 4.642 GHz up to 5.428 GHz. Considering a current consumption of 3.13 mA, with 3.0 V voltage supply.

This paper describes a 2.4 GHz single-ended switched gain low noise amplifier (SG-LNA) in a 0.35 mum SiGe BiCMOS process. In the design, specific architecture decisions were made in consideration of system-on-chip implementation. The architecture profits from a two cascode stage topology with a shunt resistive feedback in the first cascade-topology stage. The SG-LNA achieved a maximum small signal gain of 34.3 dB within input 1-dB compression point (ICP1dB) of -22 dBm in high-gain mode (HGM), a gain of 25.4 dB within ICP 1dB of -13.8 dBm in medium-gain mode (MGM) , and a minimum gain of 18.3 dB within ICP 1dB of -6.8 dBm in low-gain mode (LGM). The noise figures (NF) are 2.9 dB, 5.5 dB and 5.9 dB in HGM, MGM and LGM, respectively. Because of using a Common-Gate topology as an active input matching, the SG-LNA presented a good input and output return losses in all modes. All biases applied are active. The SG-LNA consumes a maximum DC current of 42 mA from a 3.3 volt DC supply.

A 2.4GHz front-end system design for wide spectrum WLAN applications is presented in a 0.35 μm SiGe BiCMOS Technology. This transceiver front-end contains a receive (Rx) chain with a two-stage cascode low noise amplifier (LNA) and an active down-conversion Rx mixer, and a transmit (Tx) chain composed of a Gilbert-Cell core up-conversion Tx mixer and a high-gain Driver Amplifier (DA). The high linear LNA shows a gain of 15.5 dB, an noise figure (NF) of 2.28 dB and an input- referred third-order intercept point (IP3) of +2.4 dBm with 1-dB gain bandwidth (BW) of 1.5 GHz. The single-balanced Rx mixer exhibited a gain and 1-dB gain BW of +6.8 dB and 1.5 GHz. Also a double-balanced Tx mixer with a gain and input/output return loss of -1.3dB and below -35dB, respectively, and a DA with a gain and output-referred IP3 of +29.2dB and +21.2dBm, respectively, is developed. The NF, input-referred IP3 and DC power consumption of Rx string (from antenna to Rx mixer) were achieved 4.4 dB, -15.4 dBm and 30 mW respectively. The output-referred IP3 and power consumption of Tx chain were +20.5 dBm and 125 mW, respectively.

Design and measured results of an inverse Class-F power amplifier for high efficiency operation built with an LDMOS transistor is reported in this paper. We describe the design methodology, in particular the choice of the optimum load impedance presented at the fundamental frequency and at the harmonics. Measurements performed at 1GHz on this stage power amplifier demonstrate at 2dB power gain compression; 71.9% power added efficiency, 13.2W output power and 16dB power gain. These performances, to our knowledge, represent the highest output power and gain reported for an inverse Class F power amplifier.