Indium phosphide (InP) semiconductor technology is being explored for radiofrequency (RF) applications, targeting frequencies exceeding 100 GHz, to support the next generation of 6G communication systems. When taking into account sustainability in designing this future generation, growing concerns are emerging regarding the environmental impact of communication networks and the reliance on raw materials for the production of Information and Communication Technologies (ICTs). The extraction, processing, and manufacturing of such materials and semiconductor technologies result in environmental impacts, but these impacts remain insufficiently documented. Firstly, this study evaluates the environmental impacts of manufacturing indium phosphide (InP) wafers based on industrial data and those of InP-based heterojunction bipolar transistors (HBTs) based on early-stage research data. Secondly, this study attempts to highlight the challenges posed by the increasing demand for high-tech solutions, involving raw materials, by evaluating the potential demand for indium for RF 6G applications, with a deployment scenario.

This contribution reports a successfull stacking of an AlGaN/GaN/Si high electron mobility transistor (HEMT) on co-planar-waveguide (CPW) lines fabricated on 200mm Si Trap-Rich substrate. HEMT and CPWs are interconnected with copper pillars (CuPi) using a high-yield chiplet heterogeneous integration process. Thanks to (1) the integration of low insertion loss CuPi interconnects - 0.1dB@28GHz and (2) a careful management of the heat dissipation within the 3D structure, the HEMT transistor features an output power density of 2.2W/mm @10V & a peak PAE of 41%. These RF performances are competitive to other 3D solutions found in the literature. Our industrial grade 3D assembly approach is highly promising for fabricating efficient and cost-effective 3D-RF III-V systems.

An innovative and reliable RF setup based on sine wave stress is proposed, revealing for the first time that TDDB follows a kind of power law with frequency up to 15 GHz. A physical model based on dielectric relaxation is then proposed to explain the increase in TDDB with frequency. Finally, by using an effective duty factor for RF, AC and RF sine waves can be matched to derive a universal TDDB frequency behavior that is independent of the signal waveform.

In this paper, InP/InGaAs Double Heterojunction Bipolar Transistors (DHBTs) dies based on standard process fabrication are transferred onto a Silicon interposer. The chiplet heterogeneous integration is performed with a flip-chip assembly based on Cu-Ni-SnAg mu bumps. The validity and performance evaluation of the transferred DHBTs chips is highlighted by DC and RF measurements at an optimum bias point for a frequency sweep from 250MHz to 67GHz.

A simplified methodology to link CW (Continuous Wave) RF stresses to complex mission profiles is presented in order to compare the lifetimes of different 40nm PDSOI Power Amplifier (PA) cells, versus bias and under different 5G-FR2 modulation profiles. The best lifetime is achieved when using the most complex 5G modulation due to output power/linearity constraints. VT drift correction is also identified as a powerful tool to increase transistor HCI lifetime under PA operation.

Dynamic off-state stress for RF applications is investigated via integrated test circuits to enable GHz level testing. We have performed characterization of test circuits to ensure the dynamic stress signal waveform integrity, which is verified against model simulation data. We report a x2 gain on time-to-breakdown at 1GHz against DC TDDB off-state stress. Based on extraction of $\boldsymbol{\mathrm{I}_{\text{Dlin}}}$ degradation, no frequency effect is observed from DC to 1GHz off-state stress conditions. Modeling of on-state and off-state interactions based on sum of degradations modes is then demonstrated and supported by experimental data.

We report on the development of CMOS compatible SiN/AlN/GaN MIS-HEMT process on 200mm Si substrates for Ka-band power amplification. The combination of soft gate process, gate design with reduced electric field, in- situ SiN gate dielectric, low temperature ohmic contacts, low substrate RF losses and GaN:C back-barrier leads to Ft/F MAX of 81/173GHz for 2x50μm devices with L G =150nm. At 28 GHz, the device shows performance similar to other GaN/Si technologies at V DD =10V and competitive performance with GaN/SiC at V DD =20V with PAE=41% and P SAT = 6.6W/mm.

A high voltage N-type Drain Extended MOS (NDEMOS) in 40nm RFSOI technology is presented for PA application. After a careful optimization of the drain extension, the NDEMOS transistor exhibits a f T .BV>700 GHz.V & f MAX =205GHz at L g =70nm & V DD =2V, that meet the PA requirements at mmW frequency. The large-signal RF performance of a common-source NDEMOS PA cell are assessed. It exhibits 19.2dBm of P SAT @V DD =3V, that may be further improved in a cascode configuration. With this NDEMOS device, this 300mm SOIMMW technology becomes a very cost effective platform for Front End modules (FEM) that can be competitive with other CMOS technologies (Fig. 26).

This paper studies the reliability that CMOS FD-SOI can achieved for mmWave Power Amplifier (PA) applications by means of characterizations combining RF aging tests and modeling. The technology opportunities and constraints are also shown. To demonstrate the capability of such technology, a highly rugged power-amplifier for the Ka band radio (26.5-40GHz) applications implemented in a CMOS 22FDX process is presented. By using design techniques together with an optimized supply voltage reduction, the power amplifier achieves an excellent reliability even under the worst mismatch condition (VSWR) of 7:1. These results validate the capability of the technology for highly reliable power amplifier for mmWave 5G applications.

This paper reports the VSWR (Voltage Standing Wave Ratio) ruggedness and aging measurements of two power amplifiers designed in 22FDX and 45RFSOI technologies. The PA is one of the most critical function in a front-end module as it is operating at high power and directly impacted by mismatch load. De-rating of 20% is applied on the supply voltage to ensure the operation and durability of the power amplifiers for a 10 years lifetime. The measured and modelled degradation versus time are presented and show excellent results on both technologies.

Design of reliable and high-performance radiofrequency (RF) power amplifiers (PA) in CMOS technologies is becoming more challenging due to the increasing reliability issues as we approach the scaling limit. To provide insight on hot-carrier injection (HCI) degradation at RF frequencies, this paper presents a comprehensive analysis to study HCI degradation at 28GHz with different PA architectures based on their mission profile via quasi-static approximations. Sensitivity analysis on power amplifier RF performance is also discussed to offer a better understanding on the importance of accurate device and aging behavior modeling.

This paper describes a highly rugged power-amplifier for the fifth generation (5G) FR2 new radio (NR) application implemented in a 45nm SOI process (45RFSOI). By using device stacking technique together with an optimized supply voltage reduction, the power amplifier achieves 20 dBm P sat and 23 % PAE max . A P avg of 10 dBm and a PAE avg of 8% is achieved in 64-QAM 200MHz bandwidth OFDM at EVM avg of 6.2% (-24.1dB) without the use of digital predistortion. The 4:1 VSWR measurement shows an excellent PA reliability even under the worst mismatch condition. These results enable an efficient, high power and highly reliable power amplifier for 5G applications.

RF performance and reliability of Stand-Alone (SA) MOS devices and stacked Power Amplifier (PA) cells have been deeply investigated. Ageing of device DC and RF large signal performance is very well modelled considering V T & R d drift due to Hot Carrier Injection (HCI). The PA transistor presents also a very good immunity against TDDB when operating under most of RF 5G modulations signals. Interstacked PA cell offers better trade-off performance vs reliability than Stacked and SA devices.

This work presents a SOI-LDMOS Dual-Input Doherty Power Amplifier (DPA). The proposed DPA is implemented in a 130nm SOI-CMOS technology and packaged using flip-chip on a laminate substrate. Low DPA combiner loss is achieved using high-Q inductors embedded onto the laminate. The proposed Doherty PA exhibits a measured peak output power of 30 dBm at 3.2GHz, under 3.4V voltage supply. The peak Power-Added Efficiency (PAE) is 40%, and PAE at 27dBm output power is 37%. With a 10MHz LTE signal, the linearized DPA achieves a measured ACLR of -42 dBc at 27dBm output power.

A robust and low cost Si RFSOI Power Transistor which can deliver +31dBm output power with 74% of Power Added Efficiency (PAE) and 18dB of Gain has been optimized for 4G & 5G sub-6GHz Power Amplifier (PA). By means of innovative characterizations combining RF aging tests and modeling, it is proved that this great performance can be achieved while maintaining a very high level of reliability of the PA transistor.

This paper proposes three methods of reducing device gate resistance and parasitic capacitance while boosting transconductance of MOSFET on 22FDX®. The fMAX can be improved by 50% and up to 75% for NFET and PFET with respect to a standard 2.0µm finger width layout, respectively.

22nm FDSOI is an excellent technology for IOT SOC RF/mmWave applications because of low complexity and cost, low voltage libraries, and high RF/mmWave performance 11-21. SOC applications require require high voltage devices for on chip power management (e.g. back gate bias generation), 10 transistors, sensor drivers, and off chip output drivers. These integrated circuits need technologies with high breakdown voltage (Mid.), and low on-resistance (RDSon). For switching and RF applications these devices also need to have highfr and fmAx. In this paper RFLI)MOS devices integrated into a 22nm FDS0.1 technology are described. The RFLDMOS devices include 3.3V, 5.0V, and 6.5V RFLDMOS devices. These devices have been stressed and pass 10 year life time. The 3.3V RFLDMOS devices have 55Ghz fr, 65 GRz Ayxx, 9.6V BV,i, and 1.16 mOhnkmm2 RDson" The 6.5V RFLDMOS devices have 41GHzfr, 69 GlizfmAx, I 2.2V tiVdw, and 1.86 mOhm*mm2 Rm... These devices represent the hest reported BV,6 Rosorefr and.fmvx for any RFLDMOS in an advanced node (<28nm) technology. Keywords RF, LDNIOS, FDSOI.

Fully Depleted Silicon-On-Insulator (FDSOI) technology is a strong competitor in particular for RF applications, providing high performance at low manufacturing cost. In this technology, PFET devices utilize an epitaxially grown pFET raised source/drain (pRSD). However, the pRSD structure adds to the parasitic capacitance to the gate which is a detractor of RF performance. We demonstrate a faceted epitaxial RSD process that reduces this parasitic capacitance (C-Miller) by up to -25% and further improves the already high RF pFET f(max) by +18%. In addition, we show improved defectivity (-80% non-selective growth defect count reduction), and reduced within-wafer C-Miller variability (1-sigma reduced by -42%). All of these make faceted pRSD a powerful technique to significantly improve device performance in FDSOI.

Recently, a 22nm fully depleted gate-first SOI technology (FDSOI) has shown significant promise as a low-cost alternative to FinFETs with devices that are tunable between low-leakage and high-performance regimes. [1] The 22nm FDSOI PFET utilizes a SiGe channel with epitaxial grown raised source/drain (RSD) to define the junction profile, strain the channel, and facilitate contact formation. The pRSD epitaxial growth is typically a two-layer process with a main layer of SiGe:B followed by a capping layer of Si. Because the RSD epitaxy grows along the spacer dielectric, it results in a parasitic capacitance to the Gate electrode which then contributes to the total MOSFET capacitance and degrades AC device performance. Since the thickness of the main layer as well as the cap layer has a strong influence on this parasitic capacitance (Cgd), the RSD thickness should, in theory, be kept as low as possible. This is necessary to achieve the maximum AC and RF device performance. However, decreasing the RSD thickness below a certain level has the undesirable effect of DC performance drop. Therefore, another approach is needed to decrease Cgd further without degrading the drive current. In this paper we present one of the strongest methods to increase FDSOI technology AC/RF device performance, namely faceted raised source/drain epitaxial growth. Faceted pRSD epitaxy effectively decouples the RSD height and Cgd, lowering the parasitic capacitance not by reduced total RSD height, but rather by eliminating the shared wall between the Gate and the RSD. This simple approach has two desirable outcomes: 1) low Cgd & AC performance gain, and 2) low electrical variability via suppressing the influence of RSD height variation. The primary electrical response from faceted pRSD is the lowering of Cgd up to 25% at matched DC performance at zero gate bias; and this resulted in approximately 5% ring oscillator performance and ca. 20GHz RF p-Ft improvement. Other advantages of faceted pRSD are the selectivity in epitaxial growth and electrical variability. As mentioned previously, in a typical FDX device, RSD height needs to be controlled very tightly to achieve low device variability in DC transistor parameters (Ieff, Vtsat, Ioff) and Cgd. With faceted pRSD, however, this “shared wall” between Gate and RSD is liminated. We observed that the Cgd did not respond over a range of +/- 13% in main layer thickness, which led to a tight distribution of transistor parameters. Put another way, with faceted RSD, the primary need of a tight control over the pRSD thickness is eliminated. References [1] R. Carter and et al., "22nm FDSOI technology for emerging mobile, Internet-of-Things, and RF applications," in IEDM16, San Fransisco, 2016.