The exponential growth of Internet of Things (IoT) ecosystems is driving a paradigm shift from centralized cloud computing towards decentralized architectures to mitigate latency and bandwidth constraints. While edge computing addresses some of these challenges, data transmission to local gateways still raises critical security and privacy concerns. This study explores the Compute Continuum by pushing intelligence to the extreme edge using TinyML. We propose a secure, privacy-preserving multimodal biometric authentication system designed for resource-constrained embedded devices. Our solution implements a hierarchical processing chain: an ultra-lightweight person-detection filter acts as an intelligent wake-up mechanism, followed by robust facial and voice authentication modules. Operating as a strict hierarchical pipeline, the system achieves a combined False Acceptance Rate (FAR) of just 0.12%. Experimental results on an ESP32 microcontroller demonstrate exceptional energy efficiency, requiring only 0.15 J per inference cycle. This allows the system to operate autonomously for over 39 h of continuous inference on a standard 600 mAh battery, proving the viability of standalone, privacy-by-design biometric sensors in intelligent IoT environments.

Hyperdimensional Computing (HDC) has proven effective in solving a wide range of classification tasks, often outperforming traditional Machine Learning techniques, particularly in terms of robustness to noise, low computational complexity, and suitability for hardware-efficient implementations due to its highly parallelizable algebra. However, the main barrier to HDC adoption in memory-constrained embedded systems lies in its high memory requirements, on the order of 𝒪(n× D) , where n is the number of hypervectors stored in memory and D is their dimension. In this work we present ByteHD, a lightweight compression library that reduces the memory footprint of bipolar hypervectors through efficient byte-level encoding. To test our approach, we implemented an HDC-based framework serving anomaly detection in emergency lighting devices and evaluated its impact on memory usage, execution time and classification accuracy. Experimental results show that ByteHD enables HDC implementation even on very resource constrained embedded systems of the Internet of Things, e.g. RPI Pico 2, while maintaining classification performance comparable to uncompressed implementations. These findings underscore the potential of HDC as a practical and energy-efficient learning paradigm for edge intelligence, bridging the gap between theoretical advances and real-world embedded deployments.

This paper addresses the problem of misalignment in multi-source images and proposes an efficient method for its correction using rotation techniques based on geometric transformations. This phenomenon is common in applications where sensors or cameras exhibit relative motion, generating distortions that affect the quality of subsequent analysis. In systems with computing constraints, energy consumption, or real-time operation requirements, adequate compensation for these deformations becomes essential to ensure reliable processing. In this context, a hardware-friendly architecture is proposed that implements a novel memory access strategy aimed at mitigating the negative effects of pseudo-random access inherent in geometric transformation. This strategy allows for maintaining a continuous data flow in a pipeline configuration, facilitating task parallelization and improving overall system performance. To validate the proposal, an Ultra96-V2 platform was used, a low-cost MPSoC on which a hardware architecture was developed capable of executing a bare-metal application designed to process a hyperspectral image previously loaded into DDR memory and perform its rotation and alignment in real time. Additionally, the same experiment was replicated on a Jetson Nano platform to compare hardware resources, energy consumption, execution times, and transfer rate, allowing for an evaluation of the efficiency and competitiveness of the proposed system. Finally, a comparative analysis with previously published state-of-the-art solutions is included, highlighting the advantages of the presented architecture in terms of performance, efficiency, and adaptability for embedded applications focused on multi-source image processing.

The Internet of Things (IoT) is increasingly composed of numerous sensing devices with limited power availability, which rely on energy storage solutions such as batteries or supercapacitors to sustain their operation. To ensure a reliable power supply for continuous functioning and energy replenishment, energy harvesting systems have been proposed. However, energy harvesting is not without limitations, including high equipment costs and limited feasibility in certain environments. This paper investigates a star-connected IoT network, in which the central coordinator node is equipped with a solar energy harvesting system. The harvested energy is used not only to power the coordinator’s own operations but also to activate nearby end devices via Wireless Power Transmission (WPT). Based on the estimated amount of power each end device can receive, determined by its distance from the coordinator, we propose an algorithm to compute optimal task scheduling that maximizes overall quality while satisfying the energy neutrality condition. Simulation results demonstrate the feasibility of integrating energy harvesting with WPT to efficiently power IoT devices.

This work presents an efficient hardware architecture for hyperspectral image rotation, based on a geometric matrix transformation combined with bilinear interpolation to enhance pixel accuracy. These operations are commonly used in hyperspectral image (HSI) registration processes to compensate for motion in the observed scene. The primary objective of this research is to minimize the computational resource usage of the algorithm while optimizing overall efficiency. To achieve this, a reconfigurable hardware architecture based on FPGA is employed, where the rotation algorithm is implemented as an accelerator using the Vitis HLS synthesis tool and the block flow mechanism. The FPGA-based solution with four cores achieved a latency of 0,445 ms and a throughput of 1396,9 MB/s, with an energy consumption of only 1,09 mJ. Additionally, an alternative implementation was carried out on a GPU-based architecture (Jetson Nano), resulting in a higher latency of 12,55 ms and an energy consumption of 62,75 mJ. The evaluation included energy consumption, comparison with other solutions reported in the literature, and quality metrics. The results demonstrate that the FPGA-based solution is more efficient in terms of resource utilization and energy consumption, with minimal error.

Energy neutrality in an energy harvesting Internet of Things (IoT) device ensures continuous operation of the device by trading performance with energy consumption, and a way to achieve this is by adopting a task-based model. In this model, the device embeds several alternative tasks with different ratio energy-cost/quality and a scheduler that, depending on the current energy production and battery level, runs at any time the best task to maximize the performance while guaranteeing energy neutrality. In this context, this work proposes a novel scheduling algorithm that takes into account also the stability of the device, by minimizing the leaps of quality between two consecutive tasks in the scheduling. We show by simulation and by experiments on a low-power IoT platform that the proposed algorithm greatly improves the stability of the device with respect to the state-of-the-art algorithms, with a marginal worsening of the overall quality of the tasks executed.

In image processing, a connected components algorithm is a method used to identify and label the different objects or regions present in a digital image. This algorithm can be useful for a variety of image processing tasks, such as object recognition, image segmentation, and feature extraction. This work presents the implementation of a single-pass algorithm on an FPGA-based device suitable for high-performance edge computing vision applications, the Ultra96-V2 computing board. The design and implementation of the IP core have faced challenges using the AMD-Xilinx HLS workflow and tools, which require efficient and optimized use of resources, as well as the re-engineering of the algorithm to comply with the requirements imposed by the development framework. The performance of the proposed accelerator has been thoroughly analysed using the YACCLAB benchmarking framework against a high-end and a low-end CPU. The results show an expected loss in performance due to memory and clock frequency limitations. However, concerning energy efficiency, the hardware multicore architecture outperforms the software alternatives with an improvement between two and five times, depending on the size and complexity of the images.

Lossy compression solutions have grown up during the past decades because of the increment of the data rate in the new-generation hyperspectral sensors; however, linear compression techniques include useless information on regions of little interest for the final application and, at the same time, scarce information on areas of interest. In this article, a transform-based lossy compressor, HyperLCA, has been extended to include a runtime adaptive distortion feature that brings multiple compression ratios in the same scenario. The solution has been designed to keep the same hardware-friendly feature, just as its previous version, specifically conceived to ease the deployment of the solution on reconfigurable hardware devices (FPGAs). The experiments demonstrate that the new version of the compressor is able to process 1024 × 1024 hyperspectral images and 180 spectral bands (377.5 MB) in 0.935 s with a power consumption of 1.145 W. In addition, experimental results also reveal that our architecture features high throughput (MSamples/s) and remarkable energy-efficiency (MB/s/W) tradeoffs, $10\times$ and $6\times$ greater than the best state-of-the-art solution, respectively.

The proliferation of Internet of Things (IoT) technologies in various industrial sectors has brought forth new challenges that demand attention for achieving technological maturity. One such challenge is the lack of tools for emulating the diverse components present in IoT architectures, leading to the continuous verification of each component in the chain, which proves to be a complex task. This paper addresses the verification problem in Edge/Fog IoT platforms through comprehensive end-to-end testing. To tackle this challenge, we have developed a modular IoT simulator (SimIoT) capable of efficiently emulating thousands of IoT devices in realistic scenarios, including hospitals, airports, and smart cities. The simulator allows testing of Edge platforms without the need for programming expertise. Furthermore, we demonstrate the feasibility of our simulator by presenting a use case involving the profiling of an open-source IoT platform.

As the term smart begins to move away from inflationary usage, mostly related to communication capabilities, and towards a more effective dimension, there is room for research into the systematic process of transforming the things that were not originally designed to be smart. Such a process is referred to as smartification, which evokes the digital refinement of an existing product by embedding digital technologies and smart services. The state of the art shows only a few articles that investigate such methodological approaches to provide smartness on several application domains (e.g., home appliances, buildings, cities), while the smart university domain has not been deeply faced up yet. Based on the hypothesis that a methodology synthesizes a set of suitable procedures oriented to simplify the process of measuring the degree of smartification, we propose in this work a methodology that uses technological and academic criteria for designing a tool to measure the smartification of universities. The main conclusions of this work are the following: (1) The review of the current state of the art related to smart universities and smartification reveals the need for a new vision for a more adequate and accurate assessment of the degree of smartness of universities; (2) A formal method based on Multiple-Attribute Decision Making and case study research aimed at assessing the degree of smartification within the scope of smart universities; (3) A demonstration of the feasibility and application of our method to quantify the smartification degree of the School of Computer Science (ESI) at the University of Castilla-La Mancha under the project Smart ESI; and (4) A valuable method that allows equal comparison between smart universities through a set of standardized indicators, which offers the opportunity to analyze in depth the strength and weakness, and potential achievements of any smart initiatives. To the authors' knowledge, this is the first approach aimed at assessing the extent of the smartification process in smart universities through a formal method. The outcome of this research can benefit different stakeholders: university community, researchers, and, ultimately, the digital transformation of society.

Energy neutrality of Internet of Things devices powered with energy harvesting is a concept introduced to let these devices operate uninterruptedly. A method to achieve it is by letting the device scheduling different tasks characterized by different energy costs (and quality), depending on the current energy production of the energy harvesting subsystem and on the residual battery charge. In this context, we propose a novel scheduling problem that aims at keeping the energy neutrality of the scheduling while maximizing the overall quality of the executed tasks and minimizing the leaps of quality among consecutive tasks, so to improve the stability of the output of the device itself. We propose for this problem an algorithm based on a dynamic programming approach that can be executed even on low-power devices. By simulation we show that, with respect to the state of the art, the scheduling by our algorithm greatly improve the stability of the device with a minor penalty in terms of overall quality.

Image processing pipelines involved in detecting markers from real-time video employ contour detection algorithms. Field Programmable Gate Arrays (FPGA) can provide greater computing power due to parallel processing and pipelining of the different stages in these algorithms. However, FPGA implementation of different contour detection methods remains challenging due to resource limitation and timing constraints. In this work a novel approach for a complete pipeline has been presented based on FPGA. The method used for the detection of fiducial markers from real-time video streams is based on a single-scan approach. Implementation of such pipeline into reconfigurable technology is specially challenging compared to software-oriented implementation as pointers, dynamic structures, efficient use of resources, etc. need to be considered. A driver is the need to fit the design into low-cost reconfigurable devices. To help face the related challenges of a hardware implementation High Level Synthesis (HLS) technology has been adopted, which implies reengineering of the reference algorithms. The results show a successful detection of markers over a dataset acquired in a controlled indoor environment with different resolutions at different distances. The proposal has been prototyped and tested on a Zedboard with Xilinx Zynq®-7000 SoC.

Hyperspectral imaging opens up new opportunities for masked face recognition via discrimination of the spectral information obtained by hyperspectral sensors. In this work, we present a novel algorithm to extract facial spectral-features from different regions of interests by performing computer vision techniques over the hyperspectral images, particularly Histogram of Oriented Gradients. We have applied this algorithm over the UWA-HSFD dataset to extract the facial spectral-features and then a set of parallel Support Vector Machines with custom kernels, based on the cosine similarity and Euclidean distance, have been trained on fly to classify unknown subjects/faces according to the distance of the visible facial spectral-features, i.e., the regions that are not concealed by a face mask or scarf. The results draw up an optimal trade-off between recognition accuracy and compression ratio in accordance with the facial regions that are not occluded.

Motion estimation is the cornerstone of main video compression standards, which are based on the reduction of the temporal redundancy between consecutive frames. Although the mechanism is simple, the best method, Full Search, uses a brute-force approach which is not suited for real-time applications. This work introduces a high performance architecture for performing on-the-fly full-search block matching estimation in FPGA devices, which has been modeled using C++ programming language and synthesized with Vivado HLS for a Xilinx ZC706 prototyping board. The architecture is based on a dataflow datapath and it is configurable, enabling a fast and easy exploration of the solution space. On-board results achieve a maximum performance of 743 fps, 247 fps and 110 fps for VGA, HD and FHD video resolutions, respectively, for a typical macroblock size of 16 × 16 pixels and a search area of ± 16 pixels.

High-Level Synthesis (HLS) tools help engineers to deal with the complexity of building heterogeneous embedded systems that make it use of reconfigurable technology. Also, HLS opens up a way for introducing, into the development flow of custom hardware components, techniques well known in the software industry such as Test-Driven Development (TDD). However, the support provided by HLS tools for verification activities is limited, and it is usually focused on the initial steps of the design process. In this paper, a hardware testing framework is introduced as an enabler for effortless on-board verification of components by applying the Unit Testing Paradigm and, hence, realizing TDD on reconfigurable hardware. The proposed solution comprises a hardware/software introspection infrastructure to verify modules of a system at different stages, spawning multiple abstraction levels without extra effort nor redesigning the component. Our solution has been implemented for the Xilinx ZynQ FPGA-SoC architecture and applied to the verification of C-kernels within the CHStone Benchmark. Effortless integration into the Xilinx Vivado design flow and tools is supported by a set of automatic generation scripts developed for this end. Experimental results show a considerable speedup of the verification time and unveils inaccuracies concerning the co-simulation estimation obtained by Xilinx tools when compared with the on-board latency measured by our framework.

High-Level Synthesis (HLS) tools provide facilities for the development of specialized hardware accelerators (HWacc). However, the verification stage is still the longest phase in the development life-cycle. Unlike in the software industry, HLS tools lack testing frameworks that could cover the whole design flow, especially the on-board verification stage of the generated RTL. This work introduces a framework for on-board verification of HLS-based modules by using reconfigurable systems and Docker containers with the aim to automate the verification process and preserve a clean testing environment, making the testbed reusable across different stages of the design flow. Moreover, our solution features a mechanism to check timing requirements of the HWacc. We have applied our solution to the C-kernels of the CHStone Benchmark on a Zedboard, in which the on-board verification process has been accelerated up to four times.

The amount of multimedia information on digital platforms has been increasing over the years. Social networks and the advancement of technology have been a determining factor for this event. Due to this fact, the organization, qualification and handling of this type of information has become indispensable, as well as assuring the user the quality of the service in content and execution time in the retrieval of information. This paper presents the implementation of the search process of a content-based image retrieval system, using metric spaces to perform the search and recovery of the image. The high level synthesis is used to development the IP block that will carry out the recovery process in the programmable logic. The experiments are performed on a PYNQ-Z1 board from Xilinx© and on a CPU Intel© Core i5 7th generation. The effectiveness of the implementation is supported by the results obtained.

High-Level Synthesis (HLS) allows engineers to build complex FPGA-based solutions by reducing the time-to-market; contrarily, HLS introduces some problems such as lost of control of the generated RTL and the signal observability during the development process. This fact demands an on-board debugging ecosystem so as to make HLS technology a successful approach. In this paper, HALib (Hardware Assertion Library) is introduced as a collection of synthesizable assertions that can be directly embedded into the high-level model, plus a comprehensive verification framework. HALib allows engineers to debug HLS-based modules once their have been mapped onto an FPGA by means of internal variable monitoring, avoiding any restriction regarding signal observability. Our solution has been integrated in Vivado toolchain and tested on a Zedboard with a collection of HLS kernels. The analysis of experimental results shows that the proposed solution does not incur a relevant overhead in terms of hardware resources, an increase of around 2% of FlipFlops and 1% of LUTs per assertion instantiated, neither increase the kernel delay in terms of timing.