This paper presents contour-based methods to assess mask variability. Mask certification depends on the measurement reliability and on criteria relevance. By now, ST and its maskshop partners rely mostly on CD-SEM measurements for mask certification. However, this kind of metrology has limitations and, looking at the future, we think it would be timely to search for metrology which bypass those limitations. That is why we are looking at 2D metrology ([1]), especially to area and contour measurements ([2]) on SEM images using extracted contours. Thanks to the added value of 2D metrology, we expect to assess mask variability, mask uniformity and pattern fidelity. We also take the opportunity to compare the results on two FOVs (field of view) from the images provided by mask shops. Finally, we also intend to automate the whole measurement process to make it easier to use.

Chrome migration or aging phenomenon is known for 193nm binary photomasks since a few years. 193nm irradiations and time generate an oxide growth on chrome sidewalls and then cause a non-uniform increase of critical dimensions (CD) [1], [2], [3, [4]. If not prevented or detected early enough, wafer fabs are likely to face process drifts, defectivity issues and even lower yield on wafers in the worst cases. Fortunately, some solutions have been put in place in the industry. A standard cleaning and repel service at the maskshop has been demonstrated as efficient to remove the grown materials and get the mask CD back on target. Some detection methods have been already described in literature, such as wafer CD intrafield monitoring (ACLV) [1], giving reliable results but also consuming additional SEM time with less precision than direct reticle measurement. Another approach is to monitor the CD uniformity directly on the photomask, concurrently with defect inspection for regular requalification to production for wafer fabs [5]. This enables ultimately to trigger the preventive cleanings rather than on predefined thresholds.However, may the 193nm Phase Shift Masks (PSM) be impacted too? In other words, should wafer fabs pay attention to this form of aging? Indeed, some publications [6], [7], [8] report a growth of SiO2, leading to the development of a high duration MoSi (modification of MoSi composition). This study will characterize the aging behaviour on a 193nm PSM contact hole layer, 40nm logic technology node.During this study, the aging phenomenon has been accelerated with the use of a test bench, to reach a CD increase up to 11nm after a cumulated exposure dose of 10kJ/cm(2) (equivalent to exposures of >32,000 wafers 300mm). Two dice were compared, one kept as reference without any exposure, whereas the other die was aged on the accelerated test bench. Exhaustive characterization has been performed, with CD measurements on the mask and on wafers, evaluation of lithography process windows for usual patterns and most critical features (Optical Proximity Correction hotspots). It appears that despite a consistent CD increase on the mask, the impact on wafer can be neglected, at least at this amount of exposures. Aerial CD were also analysed through a Zeiss WLCD (TM) to enable a prediction of wafer impact.An advanced inspection tool (KLA-Tencor X5.2 model) has been challenged as an inline monitoring method to detect the aging degradation on PSM. The Intensity Critical Dimension Uniformity option (iCDU (TM)) was firstly developed to provide feed-forward CDU maps for scanners intrafield corrections, from arrayed dense structures on memory masks. Due to layout complexity and differing feature types, CDU monitoring on logic masks used to pose unique challenges. CDU monitoring on logic masks is now available, the latest Delta-Die and Delta-Time options gives all the needed information, as shown in this paper. In this study, iCDU has demonstrated its ability to catch a slight degradation of CD uniformity.In the end, this study shows evidences that standard cleanings used in maskshops cannot recover the mask back to its original CD. Finally, Transmission Electron Microscopy (TEM) was used to confirm the chemical nature of the grown material on sidewalls. TEM cuts provide a comparison between a production mask (aging over many years in production) and the test mask (accelerated aging on a test bench).

In a previous work, we demonstrated that the current optical proximity correction model assuming the mask pattern to be analogous to the designed data is no longer valid. An extreme case of line-end shortening shows a gap up to 10 nm difference (at mask level). For that reason, an accurate mask model has been calibrated for a 14-nm logic gate level. A model with a total RMS of 1.38 nm at mask level was obtained. Two-dimensional structures, such as line-end shortening and corner rounding, were well predicted using scanning electron microscopy pictures overlaid with simulated contours. The first part of this paper is dedicated to the implementation of our improved model in current flow. The improved model consists of a mask model capturing mask process and writing effects, and a standard optical and resist model addressing the litho exposure and development effects at wafer level. The second part will focus on results from the comparison of the two models, the new and the regular. (C) 2016 Society of Photo-Optical Instrumentation Engineers (SPIE)

In a previous work [1] we demonstrated that current OPC model assuming the mask pattern to be analogous to the designed data is no longer valid. Indeed as depicted in figure 1, an extreme case of line-end shortening shows a gap up to 10 nm difference (at mask level). For that reason an accurate mask model, for a 14nm logic gate level has been calibrated. A model with a total RMS of 1.38nm at mask level was obtained. 2D structures such as line-end shortening and corner rounding were well predicted using SEM pictures overlaid with simulated contours. The first part of this paper is dedicated to the implementation of our improved model in current flow. The improved model consists of a mask model capturing mask process and writing effects and a standard optical and resist model addressing the litho exposure and development effects at wafer level. The second part will focus on results from the comparison of the two models, the new and the regular, as depicted in figure 2.

The understanding and control of the intra-field overlay budget becomes crucial particularly after the introduction of multi-patterning applications. The intra-field overlay budget is built-up out of many contributors, each with its own characteristic. Some of them are (semi-) static like the reticle writing error (RWE) fingerprint, the scanner lens fingerprint, or the intra-field processing signature. Others are more dynamic. Examples are reticle heating and lens heating due to the absorption of a small portion of the exposure light. Ideally, all overlay contributors that are understood and known could be taken out of the feed-back control loop and send as feed-forward corrections to the scanner. As a consequence, only non-correctable overlay residuals are measured on the wafer.In the current work, we have studied the possibility to characterize the reticle writing error fingerprint by an off-line position measurement tool and use this information to send feed-forward corrections to the ASML TWINSCAN (TM) exposure tool. The current work is an extension of the work we published earlier. To this end, we have selected a reticle pair out of 50 production reticles that are used to manufacture a 28-nm technology device. These two reticles are special in the sense that the delta fingerprint contains a significant higher order RWE signature. While previously only the linear parameters were sent as feed-forward corrections to the ASML TWINSCAN (TM) exposure tool, this time we additionally demonstrate the capability to correct for the non-linear terms as well. Since the concept heavily relies on the quality of the off-line mask registration measurements, a state-of-the-art reticle registration tool was chosen. Special care was taken to eliminate any effects of the tool induced shifts that may affect the quality of the measurements. The on-wafer overlay verification measurements were performed on an ASML YieldStar metrology tool as well as on a different vendor tool.In conclusion, we have extended and proven the concept of using off-line reticle registration measurements to enable higher order feed-forward corrections the ASML TWINSCAN (TM) scanner. This capability has been verified by on-wafer overlay measurements. It is demonstrated that the RWE contribution in the overlay budget can be taken out of the feedback control loop and sent as feed-forward corrections instead. This concept can easily be extended when more scanner corrections become available.

Patterning process control has undergone major evolutions over the last few years. Critical dimension, focus, and overlay control require deep insight into process-variability understanding to be properly apprehended. Process setup is a complex engineering challenge. In the era of mid k1 lithography (>0.6), process windows were quite comfortable with respect to tool capabilities, therefore, some sources of variability were, if not ignored, at least considered as negligible. The low k1 patterning (<0.4) era has broken down this concept. For the most advanced nodes, engineers need to consider such a wide set of information that holistic processing is often mentioned as the way to handle the setup of the process and its variability. The main difficulty is to break down process-variability sources in detail and be aware that what could have been formerly negligible has become a very significant contributor requiring control down to a fraction of a nanometer. The scope of this article is to highlight that today, engineers have to zoom deeper into variability. Even though process tools have greatly improved their capabilities, diminishing process windows require more than tool-intrinsic optimization. Process control and variability compensations are major contributors to success. Some examples will be used to explain how complex the situation is and how interlinked processes are today. (C) 2015 Society of Photo-Optical Instrumentation Engineers (SPIE)

The on-product overlay specification and Advanced Process Control (APC) are getting extremely challenging particularly after the introduction of multi-patterning applications like Litho-Etch-Litho-Etch (LELE). While the Reticle Writing Error (RWE) contribution could be marginalized for quite some time in the layer-to-layer overlay budget, it will become one of the dominating overlay contributors when the intra-layer overlay budget is considered. While most of the overlay contributors like wafer processing, scanner status, reticle transmission, dose, illumination conditions drop out of the intra-layer overlay budget, this is certainly not the case for reticle to reticle writing differences. In this work, we have studied the impact of the RWE on the on-product overlay performance. We show that the RWE can be characterized by an off-line mask registration tool and the modelled results can be sent as feed-forward corrections to the ASML TWINSCANTM. By doing so, the overlay control complexity (e.g. send-ahead wafers, APC settling time) can be reduced significantly. Off-line characterization enables that all reticles virtually become equal after correction (at least to the level of correction capability of the scanner). This means that all higher order RWE contributions (currently up to a third order polynomial) can be removed from the fingerprint. We show that out of 50 production reticles (FEOL, 28-nm technology), 30% can be improved on residual level when non-linear feed-forward corrections are considered as well. The additional benefit of feeding forward linear corrections to the scanner is even higher: it is anticipated that a large portion of the APC variation might find its origin in the RWE contribution. In order to send feed-forward corrections to the scanner, we obviously rely on the quality of the off-line RWE measurements. These measurements are usually provided by a registration tool at the mask shop. To secure the quality, an independent experimental verification test was developed to check if off-line RWE measurements can be used as feed-forward corrections to the scanner. The test has been executed on an ASML NXT: 1950i scanner and was designed such to isolate the reticle writing error contribution. The match between the off-line measurements and the experiment is striking.

Standard OPC models consist of a physical optical model and an empirical resist model. The resist model compensates the optical model imprecision on top of modeling resist development. The optical model imprecision may result from mask topography effects and real mask information including mask ebeam writing and mask process contributions. For advanced technology nodes, significant progress has been made to model mask topography to improve optical model accuracy. However, mask information is difficult to decorrelate from standard OPC model. Our goal is to establish an accurate mask model through a dedicated calibration exercise. In this paper, we present a flow to calibrate an accurate mask enabling its implementation. The study covers the different effects that should be embedded in the mask model as well as the experiment required to model them.

Advanced CMOS nodes require more and more information to get the wafer process well setup. Process tool intrinsic capabilities are not sufficient to secure specifications. APC systems (Advanced Process Control) are being developed in waferfab to manage process context information to automatically adjust and tune wafer processing. The APC manages today Run to Run component from and between various process steps plus a sub-recipes/profiles corrections management. This paper will outline the architecture of an integrated/holistic process control system for a high mix advanced logic waferfoundry.

193nm binary photomasks are still used in the semiconductor industry for the lithography of some critical layers for the nodes 90nm and 65nm, with high volumes and over long periods. However, these 193nm binary photomasks can be impacted by a phenomenon of chrome oxidation leading to critical dimensions uniformity (CDU) degradation with a pronounced radial signature. If not detected early enough, this CDU degradation may cause defectivity issues and lower yield on wafers. Fortunately, a standard cleaning and repellicle service at the mask shop has been demonstrated as efficient to remove the grown materials and get the photomask CD back on target.Some detection methods have been already described in literature, such as wafer CD intrafield monitoring (ACLV), giving reliable results but also consuming additional SEM time with less precision than direct photomask measurement. In this paper, we propose another approach, by monitoring the CDU directly on the photomask, concurrently with defect inspection for regular requalification to production for wafer fabs. For this study, we focused on a Metal layer in a 90nm technology node. Wafers have been exposed with production conditions and then measured by SEM-CD. Afterwards, this photomask has been measured with a SEM-CD in mask shop and also inspected on a KLA-Tencor X5.2 inspection system, with pixels 125 and 90nm, to evaluate the Intensity based Critical Dimension Uniformity (iCDU) option. iCDU was firstly developed to provide feed-forward CDU maps for scanner intrafield corrections, from arrayed dense structures on memory photomasks. Due to layout complexity and differing feature types, CDU monitoring on logic photomasks used to pose unique challenges.The selection of suitable feature types for CDU monitoring on logic photomasks is no longer an issue, since the transmitted intensity map gives all the needed information, as shown in this paper. In this study, the photomask was heavily degraded after more than 18,000 300mm wafers exposed and the cleaning brought it back almost to its original state after manufacture. Wafer CD, photomask CD and iCDU results can be compared, before and after a standard mask shop cleaning. Measurement points have be chosen in logic areas and SRAM areas, so that their respective behaviours can be studied separately. Transmitted maps before and after cleaning were analysed in terms of CD shift and CDU degradation. The delta map shows a nice correlation with photomask CD shift. iCDU demonstrated the capability to detect a reliable CD range degradation of 5nm on photomask by a comparison between a reference inspection and the current inspection. Die to die inspection mode provides also valuable data, highlighting the degraded chrome sidewalls, more in the photomask centre than on the edges. Ultimately, these results would enable to trigger the preventive cleanings rather than on predefined thresholds. The expected gains for wafer fabs are cost savings (adapted cleanings frequency), increased photomask availability for production, longer photomask lifetime, no additional SEM time neither for photomask nor on wafer.

The main difficulty related to DoseMapper correction is to generate an appropriate CD datacollection to feed DoseMapper and to generate DoseRecipe in a user friendly way, especially with a complex process mix.We could heavily measure the silicon and create, in feedback mode, the corresponding DoseRecipe. However, such approach in a logic fab becomes a heavy duty due to the number of different masks / product / processes. We have observed that process CD variability is significantly depending on systematic intrawafer and intrafield CD footprints that can be measured and applied has generic pre-correction for any new product/mask process in-line. The applied CD correction is based on a CD (intrafield: Mask + Straylight & intrawafer: Etch Bias) variability "model" handled by the FAB APC (Advanced Process Control).Individual CD profile correction component are generated "off-line" (1) for Intrafield Mask via automatic CD extraction from a Reticle CD database (2) for Intrafield Straylight via a CD "model" (3) for Intrawafer Etch Bias via engineering input based on process monitoring.These CD files are handled via the FAB APC/automation system which is remotely taking control of DoseMapper server via WEB services, so that CD profiles are generated "off-line" (before the lot is being processed) and stored in a profile database while DoseRecipes are created "real-time" on demand via the automation when the lot comes to the scanner to be processed. DoseRecipe and CD correction profiles management is done via the APC system.The automated DoseRecipe creation is now running since the beginning of 2011 contributing to bring both intrafield and intrawafer GATE CDu below 1nm 3sigma, for 45/40 & 28nm nodes.

The new generations of photomasks are seen to bring more and more challenges to the mask manufacturer. Maskshops face two conflicting requirements, namely improving pattern fidelity and reducing or at least maintaining acceptable writing time. These requirements are getting more and more challenging since pattern size continuously shrinks and data volumes continuously grows. Although the classical dose modulation Proximity Effect Correction is able to provide sufficient process control to the mainstream products, an increased number of published and wafer data show that the mask process is becoming a nonnegligible contributor to the 28nm technology yield. We will show in this paper that a novel approach of mask proximity effect correction is able to meet the dual challenge of the new generation of masks. Unlike the classical approach, the technique presented in this paper is based on a concurrent optimization of the dose and geometry of the fractured shots. Adding one more parameter allows providing the best possible compromise between accuracy and writing time since energy latitude can be taken into account as well. This solution is implemented in the Inscale software package from Aselta Nanographics. We have assessed the capability of this technology on several levels of a 28nm technology. On this set, the writing time has been reduced up to 25% without sacrificing the accuracy which at the same time has been improved significantly compared to the existing process. The experiments presented in the paper confirm that a versatile proximity effect correction strategy, combining dose and geometry modulation helps the users to tradeoff between resolution/accuracy and e-beam write time.

With the next technology nodes 193nm lithography is pushed to its utmost limits. The industry is forced to print at low k1 factor which goes along with a high MEEF. Additionally, new blank materials are being introduced for smaller nodes. From 4x node and beyond, global CD uniformity on wafer is getting more critical and becomes key factor to ensure a high yield in chip production. Advanced process control is required and correction strategies are applied to maintain tight wafer CD uniformity. Beside other parameters, like scanner and etch process, mask CD uniformity is one main contributor to the intra-field CD on wafer. To enable effective CDU correction strategies it is necessary to establish a mask CD uniformity metrology which shows a good correlation to wafer prints. Especially for logic pattern mask uniformity measurements to control intra-field CD uniformity becomes challenging.In this paper we will focus on mask CD uniformity measurement for logic application utilizing WLCD, which is based on aerial image technology. We will investigate 40nm node and 28nm node gate masks using 6% MoSi phase shifting mask and MoSi binary mask respectively. Furthermore, we will correlate the mask CD uniformity data to wafer data to evaluate the capability of WLCD to predict the intra-field wafer CD uniformity correctly in order to support feed-forward correction strategies. We will show that WLCD shows an excellent correlation to wafer data. Additionally, we will provide an outlook on logic contact-hole masks showing first CD uniformity data and wafer correlation data.

Full chip verification has become a key component of the optical proximity correction (OPC) methodology over the last decade. Full field verification to catch cross-field effects based on scanner information is becoming increasingly important in lithography verification. Lithographic Manufacturing Check (LMC) performed with the Brion Tachyon engine, which is the industry reference tool, now provides the capability to predict wafer CD variations across the entire field through process windows. LMC is catching and reporting weak lithographic points having small process windows or excessive sensitivities to mask errors based on the simulation from models with ASML scanner specific parameters.ASML scanner intra-field information such as dose, focus, flare, illuminator map, aberration data or mask bias map can be integrated into the LMC run to create an across-field verification and can improve the accuracy of the prediction at different field locations. In this study we compare such across-field LMC verification with a reference LMC without any scanner specific data.Scanner information was loaded into the LMC model by using the Scanner Fingerprint File (SFF) functionality. Various across field LMC runs using scanner information have been performed and analysed to identify critical design hotspots or scanner drifts and compared with wafer measurement.Full field Tachyon LMC results on 40nm Poly and 28nm Metal1 layer are presented. The goal is to investigate the impact of mask, lens aberrations, illuminator, dose and focus map. This investigation includes wafer validation of the methodology on identified critical hot spots.

Optical lithography stays at 193nm with a numerical aperture of 1.35 for several more years before moving to EUV lithography. Utilization of 193nm lithography for 45nm and beyond forces the mask shop to produce complex mask designs and tighter lithography specifications which in turn make process control more important than ever. High yield with regards to chip production requires accurate process control. Critical Dimension Uniformity (CDU) is one of the key parameters necessary to assure good performance and reliable functionality of any integrated circuit. There are different contributors which impact the total wafer CDU, mask CD uniformity, resist process, scanner and lens fingerprint, wafer topography, etc.In this paper, the wafer level CD metrology tool WLCD of Carl Zeiss SMS is utilized for CDU measurements in conjunction with the CDC tool from Carl Zeiss SMS which provides CD uniformity correction. The WLCD measures CD based on proven aerial imaging technology. The CDC utilizes an ultrafast femto-second laser to write intra-volume shading elements (Shade-In ElementsTM) inside the bulk material of the mask. By adjusting the density of the shading elements, the light transmission through the mask is locally changed in a manner that improves wafer CDU when the corrected mask is printed.The objective of this study is to evaluate the usage of these two tools in a closed loop process to optimize CDU of the mask before leaving the mask shop and to ensure improved intra-field CDU at wafer level. Mainly we present the method of operation and results for logic pattering by using these two tools.(C) (2012) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.

193nm binary photomasks are still used in the semiconductor industry for the lithography of some critical layers for the nodes 90nm and 65nm, with high volumes and over long period. These 193nm binary masks seem to be well-known but recent studies have shown surprising degrading effects, like Electric Field induced chromium Migration (EFM) [1] or chromium migration [2] [3] . Phase shift Masks (PSM) or Opaque MoSi On Glass (OMOG) might not be concerned by these effects [4] [6] under certain conditions. In this paper, we will focus our study on two layers gate and metal lines. We will detail the effects of mask aging, with SEM top view pictures revealing a degraded chromium edge profile and TEM chemical analyses demonstrating the growth of a chromium oxide on the sidewall. SEMCD measurements after volume production indicated a modified CD with respect to initial CD data after manufacture. A regression analysis of these CD measurements shows a radial effect, a die effect and an isolated-dense effect. Mask cleaning effectiveness has also been investigated, with sulphate or ozone cleans, to recover the mask quality in terms of CD. In complement, wafer intrafield CD measurements have been performed on the most sensitive structure to monitor the evolution of the aging effect on mask CD uniformity. Mask CD drift have been correlated with exposure dose drift and isolated-dense bias CD drift on wafers. In the end, we will try to propose a physical explanation of this aging phenomenon and a solution to prevent from it occurring.

Since 2008, we have been presenting some papers regarding CMOS 45nm logic gate patterning activity to reduce CD dispersion. After a global CD budget evaluation at SPIE08, we have been focusing on Intrafield CD corrections using Dose MapperTM. The story continues and since then we have pursued our intrafield characterisation and focus on ways to get Dose MapperTM dose recipe created before the first silicon is coming. In fact 40nm technology is already more demanding and we must be ready with integrated solutions for 32/28nm node. Global CD budget can be divided in Lot to Lot, Wafer to Wafer, Intra wafer and Intra field component. We won't talk here about run to run solutions which are put in place for Lot to Lot and Wafer to Wafer. We will emphasize on the intrafield / intrawafer process corrections and outline process compensation control and strategy. A lot of papers regarding intrafield CD compensation are available in the litterature but they do not necesserally fit logic manufacturing needs or possibilities. We need to put similar solutions in place which are comprehensive and flexible. How can we correct upfront an Etch chamber CD profile combined with a mask and scanner CD signature? How can we get intrafield map from random logic devices? This is what we will develop in this paper.

Microlens arrays are used on CMOS image sensors to focus incident light onto the appropriate photodiode and thus improve the device quantum efficiency. As the pixel size shrinks, the fill factor of the sensor (i.e. ratio of the photosensitive area to the total pixel area) decreases and one way to compensate this loss of sensibility is to improve the microlens photon collection efficiency. This can be achieved by developing zero-gap microlens processes. One elegant solution to pattern zero-gap microlenses is to use a grayscale reticle with varying optical densities which locally modulate the UV light intensity, allowing the creation of continuous relief structure in the resist layer after development. Contrary to conventional lithography for which high resist contrast is appreciated to achieve straight resist pattern profiles, grayscale lithography requires smooth resist contrast curve. In this study we demonstrate the efficiency of grayscale lithography to generate sub-2 mu m diameter microlens with a positive-tone photoresist. We also show that this technique is resist and process (film thickness, development normality and exposure conditions) dependent. Under the best conditions, spherical zero-gap microlenses as well as aspherical and off-axis microlenses, which are impossible to obtain with the conventional reflow method, were obtained with satisfying process latitude.

In microelectronic industry, mainly from the 65nm node, phase shift photomasks (PSM) are increasingly used for critical layers, optical properties of the shifter (MoSi) giving a better control of critical dimensions (CD) in photoresist. Fab-users and maskshops have committed on specifications that restrict phase and transmission variations within certain limits. The goal of this study is to validate and/or update these previously admitted limits. A specific test reticle has been jointly designed with several structures representative of 65nm and 45nm nodes and then manufactured with a specific process in order to voluntarily degrade the phase and transmission uniformity within the mask. Knowing all CD and their related phase and transmission on mask, CD variations seen on wafers have been directly linked to phase and transmission variations. In parallel, rigorous simulations have been performed using Panoramic software in order to predict effects of phase and transmission variations on wafer. This reticle has been also used for early studies to evaluate the impact of phase and transmission variations on optical proximity correction (OPC) model.

The paper describes a new approach of evaluating isolated opaque defects, as well as CD-like defects on hole layer, using features available on the inspection tool. This eliminates further verifications on specific tools, which would result in their overloading and in time consuming, with a potential negative impact on the delivery time of any product going through such processes. In the first case the method consists of associating the effect of a cluster of assist bars to that of isolated opaque defects, considering their size and position on the layout of the mask. In case of CD-like defects on holes the evaluation is based on a thorough characterization of the performance of the Litho2 detector of the Terascan T576 and its further verification with the AIMS readings.