Despite of the fact that thousands of CD-SEM (critical dimension scanning electron microscope) images are acquired in a daily basis in a fab, limited metrology is performed. Usually these images will not serve other purposes after they are collected and measured, but as they are stored, post-process analysis can be applied. Initially, most of these images are used to perform CD metrology, even though many other types of metrics could be extracted from the same images, especially when using contour metrology. In this paper two use cases will be explored, where contour-based image processing is performed on typical inline metrology targets. In both cases, initial intended metric was CD but thanks to contour based image computing, complementary information can be extracted. In the first use case, CD and overlay metrics can be extracted, while in the second CD, etch slanting and asymmetry analysis is performed across the wafer. Contour-based metrology offers new capabilities to dissociate several layers (e.g. via and line) or elements (e.g. top and bottom) in the image so that interlayer and intralayer metrics, other than width dimensions, can be computed. Besides, a solution not integrated in the tool provides excellent versatility to re-process images, thus allowing the obtention of new metrics, which can be very helpful also for retro-analysis.

In semiconductor fabs, electron microscopes are key equipment for metrology, failure analysis, physical characterization and defect review classification. In a wafer fab like ST Crolles 300mm, CDSEMs are generating more than 20 Million of images per year. The image is by itself a raw material on which the metrology is performed. It is needed to get access to CD which is very often a single value extracted. If the CD is in specification, it is very unlikely that someone will look at the picture. If someone would do so in a systematic way, it would see that there is much more information available in the image than a single CD value. Unfortunately, most of this information passes under the radar of SPC charts and is somehow wasted. This paper presents results obtained by CDSEM image contour analysis from various kind of technologies and applications in manufacturing in our fab. These results show that images contain significant amounts of information that can be extracted and analyzed using an efficient contour extraction and analysis toolbox. Process variability of complex shapes can be shown, robust layer to layer metrics can be computed, pattern shifting, shape changes, image quality and many others too. This opens new possibilities for process control and process variability monitoring and mitigation.

Critical dimension and overlay measurements have become a key challenge in microelectronics process control, and the weight of metrology in the success of a patterning technique is increasing. For the 14 nm node, the limit of scanner resolution can be overcome by double patterning, which requires a maximum overlay variability of 3 nm between the two reticles of the first metal level. In the double patterning case of metal layers, critical dimension of line spaces and overlay are no longer independent. In this paper, the possibility of a common measurement after the second lithography is studied. Scatterometry has been used to fit successfully the critical dimension of the two sublevels. As sensitivity to overlay is too low in device-like target, a strategy has been implemented from diffraction-based overlay measurement. So it becomes possible to provide information on the lithography step quality before the second etch process to enable rework if necessary. Finally a scatterometry target has been designed to fit simultaneously the two critical dimensions and overlay. This target, which is designed to maximize overlay sensitivity, has been placed in the next 14 nm CMOS product and is expected to make this scatterometry method even more attractive.

The patterning of narrow trenches in porous SiOCH with a metallic hard mask can lead to the undulation of the dielectric lines between the trenches, also called wiggling. This phenomenon is attributed to the relaxation of the residual stress of the highly compressive hard mask by deforming the mechanically weak porous dielectric. This work analyses the parameters (titanium nitride stress and thickness, lines width and height, and materials Young modulus) potentially responsible for dielectric lines undulations using finite element mechanical modeling. These simulations are experimentally validated.

Advanced CMOS nodes require more and more information to get the wafer process well setup. Process tool intrinsic capabilities are not sufficient to secure specifications. APC systems (Advanced Process Control) are being developed in waferfab to manage process context information to automatically adjust and tune wafer processing. The APC manages today Run to Run component from and between various process steps plus a sub-recipes/profiles corrections management. This paper will outline the architecture of an integrated/holistic process control system for a high mix advanced logic waferfoundry.

Current process tool performances are getting significantly enhanced by the adoption of advanced process correction application such as DoseMapper for CD or high order overlay correction for overlay. These process control capabilities need appropriate sampling to be efficient. Usually for in field metrology sampling we used to operate with metrology targets placed inside the scribe lines, however in this case the larger the chip the less scribe lines we have and the less relevant is the intrafield sampling. As ST is an IDM we have the opportunity to share with our design division this process control problematic. Since 45/40nm node we have started to put in place the so-called EMET (Embedded Metrology Target) strategy which consists in in-design metrology targets placement. Initially these targets were placed using tiling tools but it soon appeared to be not efficient and even impossible when we talk about targets involving complex metal stack.This papers talks about our current embedded metrology target strategy which has been adapted to enable appropriate target placement for CD and overlay for all critical layers from active to via/metal's. Solutions needed to be put in place to (i) keep the circuit safe by using Design Rule clean metrology targets, (ii) be highly visible by the designers by placing targets at chip floor planning definition (iii) be upgradable by enabling target re-designs without impact on chip design version.

In this paper, we study how to boost the performance of FDSOI devices with High-K and Single Metal gate by using the combination of UTBOX GP and local back biasing integrated with our hybrid process. The interest of local back biasing is highlighted in term of VT modulation and power management study on the 45 nm 0.374 μm2 bitcells and on the ESD functionality as compared to bulk technology.

The use of a metallic hard mask approach for porous dielectric film integration implies for patterning processes, different difficulties like dimensional control, bottom line roughness and residue formation or chamber conditioning. In this paper we propose to present these issues and associated solutions for p-SiOCH integration in dual damascene structure using a trench first metallic hard mask approach.

The choice of copper/low-k interconnect architectures is instrumental in achieving high device performances. Today, the implementation of porous low-k materials becomes mandatory in order to compensate metal resistance increase upon RC product. However, their introduction, which was initially planned for the 65nm technological node, was delayed to 45nm node due to integration issues. Using an integration strategy which combines porous SiOCH materials and metal hard masks, the difficulties and possible solutions are presented in this paper with emphasis on plasma etching.

The etching of sub-100-nm porous dielectric trenches has been investigated using an organic mask. The etching process that is performed in an oxide etcher is composed of three steps: a thin dielectric antireflective coating (DARC) layer (silicon containing layer) is etched in the first step, the organic mask [carbon-based layer (CL)] is opened in the second step, and the dielectric layer is etched in the last step. The DARC layer is open in a fluorocarbon-based plasma (CF4∕Ar∕CH2F2) and the main critical dimension issue is the critical dimension control of the trench, which can be adjusted by controlling the amount of polymer generated by the etching chemistry (% of CH2F2). The CL is etched using NH3 based plasmas, leading to straight trench profiles. For dielectric patterning, the etch process results from a delicate trade-off between passivation layer thickness and mask faceting. This is driven by the polymerizing rate of the plasma (% of CH2F2) which controls the trench width. Using an optimized etchin...

Porous SiCOH materials integration for integrated circuits faces serious challenges such as roughening during the etch process. In this study, atomic force microscopy is used to investigate the kinetics of SiCOH materials roughening when they are etched in fluorocarbon plasmas. We show that the root mean square roughness and the correlation length linearly increase with the etched depth, after an initiation period. We propose that: (1) during the first few seconds of the etch process, the surface of porous SiCOH materials gets denser. (2) Cracks are formed, leading to the formation of deep and narrow pits. (3) Plasma radicals diffuse through those pits and the pore network and modify the porous material at the bottom of the pits. (4) The difference in material density and composition between the surface and the bottom of the pits leads to a difference in etch rate and an amplification of the roughness. In addition to this intrinsic roughening mechanism, the presence of a metallic mask (titanium nitride) can lead to an extrinsic roughening mechanism, such as micromasking caused by metallic particles originating form the titanium nitride mask.

This work focuses on the impact of oxidizing (O2) and reducing plasma ashing chemistries (NH3, CH4) on the modifications of dielectric materials in a porous or an hybrid state (SiOCH matrix+porogen). The plasma ashing processes have been performed on blanket wafers using O2, NH3, and CH4 based plasmas. The modifications of the remaining film after plasma exposures have been investigated using different analysis techniques such as x-ray photoelectron spectroscopy, infrared spectroscopy, x-ray reflectometry, and porosimetric ellipsometry. For the porous material the authors have shown that NH3 and O2 plasmas induce carbon depletion and moisture uptake while the CH4 plasma only leads to important carbon depletion without moisture uptake and to the formation of a thin carbon layer on the surface. For the hybrid material, no significant material modification is evidenced with the O2 plasma while an important methyl depletion and porogen degradation are observed with reducing chemistries such as CH4 and NH3 plasmas. The impact of the porogen on the film modification and the value of the dielectric constant will be presented and discussed.