This paper presents a methodology of calibration to reduce the linearity error of gain in Time amplifier (TA). We divide the input range to several segments and calculate the average of maximum and minimum TA gain in each segment. We also have the checking points to check the width of input interval and decide which segment and corresponding TA gain is for the measured interval. The checking point is the maximum interval in each segment. The input range for each segment is 50 ps, that is, 0-50 ps is the first segment, 50-100 ps is the second segment, and so on. For the TA which the measured range is 700 ps, we divide the range to 14 segments and there is its corresponding TA gain in each segment. The gain error will be reduced from 0.82% to 0.33% and the distortion caused by gain error will be reduced from 5.74 ps to 0.51 ps.

This brief discusses an oscillator-based capacitive 3-D touch-sensing circuit for mobile devices. The proposed 3-D touch sensor uses correlated double sampling to achieve a high sensing resolution in the Z-direction and employs bootstrapping circuitry to reduce the mobile screen's interchannel-coupling effects. Additionally, to reduce chip area and assembly, the sensing oscillator is implemented with inverter-based active resonators instead of using either on-or off-chip inductors. The prototyped 3-D touch sensor is fabricated using 65-nm CMOS process technology and consumes an area of 2 mm(2), with a 2.3-mW power consumption from a 1-V power supply. Measured together with a 3.4 '' HTC standard mobile screen, the sensor achieves an 11-cm Z-direction sensing range with a 1-cm resolution, demonstrating the potential implementation of 3-D finger position sensing in a mobile device.

Contactless (3D) touch sensors, when integrated with displays, offer many advantages over that of conventional touch-panel screens by offering a more hygienic and a more immersive & interactive human/machine interface for 3D user experiences [1]. While significant progress has been made in developing 3D contactless touch sensors for larger television and monitor type displays [2-3], the technology has yet to be infused into space- and battery-constrained mobile devices (i.e., tablets and smartphones). For successful insertions into these systems, a paradigm shift in touch-sensor system design is essential to enable seamless sensing operations with smaller-size, more tightly spaced, strongly coupled, and highly resistive display electrodes. In addition, any successful 3D sensing solution for mobile devices must consume low power and small silicon area to be compatible with limited battery and space resources.

This paper presents a 95 GHz centimeter scale navigation system which allows a unmanned ground vehicle (UGV) or possibly even aerial vehicle (UAV) to navigate through a highly cluttered environment and follow a safe obstacle-free pathway to a desired goal. The navigation system defines multiple pathways using mm-wave base-stations called path generators and then uses a single CMOS SoC containing a receiver, ADC and an FFT processor to detect and navigate these pathways. The demonstrated confined pathway SoC (CP-SoC) occupies 5.4mm2 of silicon area in 65nm technology, and consumes only 199 mW, making it suitable for lightweight payloads associated with UAVs and UGVs.

This paper presents an all-digital standard cell SR-Latch based time amplifier (TA) with a variable gain of 6X and 12X. In this TA, a two-stage gain selection unit is applied to enable the TA to select either the high gain for short input pulse intervals or the low gain for long input pulse intervals. The time amplification gain is 6 in the input range of -700ps ~700ps, and reaches 12 if the input range is -300~300ps. We present a design that automatically detects the input pulse and switches to the proper TA gain. By applying the proposed TA, a standard cyclic TDC implemented in a UMC CMOS 65-nm process shows the resolution improved from 1.6ps to 0.8 ps.

The paper presents a 2.2 GS/s (1.1 GHz Nyquist bandwidth), 188 mW 512-channel spectrometer processor developed to support of future science observations on NASA planetary missions, where payload size, weight, and power consumption are extremely limited. The presented spectrometer processor chip contains a pair of 7 bit ADC IQ converters coupled with a 512 point PSD processor, and averaging accumulator, allowing it to be sensitive enough to detect trace gases like NH3, HCN, and CO2 when coupled to the appropriate band RF front-end receiver. The bandwidth and resolution of the presented processor make it suitable for exploring the composition of planets, moons and their atmospheres throughout our solar system.

This paper presents a scalable transmit phase array operating at 140 GHz which employs a local PLL reference generation system. Unlike traditional CMOS phase arrays, this enables the array to be formed over multiple chips while avoiding the challenges of distributing mm-wave signals between them. The prototype chip consumes 131 mW of power and occupies 1.95 mm2 of chip area when implemented in 65 nm CMOS technology.

A 10-bit 2-GS/s mixed-signal baseband (BB) circuit, which enables a self-healing 60-GHz 4-Gb/s radio-on-chip implemented in a 65-nm complementary metal-oxide semiconductor, is described. The BB circuit autonomously senses and optimizes transmitter (TX) P-1dB, OIM3, and image suppression, reducing the yield loss because of process variations. On-chip test tones are generated using a 10-bit 2-GS/s current-steering digital-to-analog converter (DAC) and direct digital frequency synthesizer (DDFS). Using the generated test tones, the aforementioned impairments are measured by an envelope detector at the power amplifier output. Based on this information, the programmable digital IQ phase amplitude and offset controller (IQ_CTRL) in the BB circuit improves the TX image suppression from -32.4 to -42.6 dBc, and digital control signals generated by the on-chip self-healing controller heal the TX P-1dB and OIM3 from 9.5 to 13.2 dBm and from -32.5 to -40 dBc, respectively. In terms of achieving the target specifications, namely, TX image suppression < -40 dBc, OIM3 < -40 dBc, and P-1dB > 10 dBm, healing increases yield on ten dies from 0% to 100%. The BB circuit consumes only 49 mW, of which 37 mW comes from the DACs and 12 mW from the DDFS and the IQ_CTRL.

This paper presents a complete 2x2 phased array transmitter system operating at W-band (90-95 GHz) which employs a PLL reference time-shifting approach instead of using traditional mm-wave phase shifters. PLL reference shifting enables a phased array to be distributed over multiple chips without the need for coherent mm-wave signal distribution between chips. The proposed phased array transmitter system consumes 248 mW per array element when implemented in a 65 nm CMOS technology.

This article discusses a self-healing 60-GHz transceiver architecture which employs information collected from on-chip sensors to intelligently adjust various tuning knobs and significantly improve the post-healing performance yield.

A D-band CMOS transmitter is presented with an integrated injection-locked frequency-tripling synthesizer, digital control, and an on-chip antenna. It employs an IF feed-forward pre-distortion scheme, which improves gain compression of the transmitter to provide an overall higher linearity gain profile, allowing reduced power back-off for higher peak-to-average modulation schemes. The integrated D-band transmitter consumes 347 mW and occupies 1800× 1500 μm of silicon area. The proposed transmitter delivers 0.4 dBm of effective isotropic radiated power with a saturated power on-chip of at least 12.2 dBm. The transmitter has a peak power-added efficiency (PAE) of 4.8% with power delivered to the antenna and a peak PAE of 0.31% when considering radiated power.

A CMOS D-band 135-150 GHz transmitter is presented with integrated digital control and on-chip antenna. The proposed transmitter employs an IF feed-forward compensation scheme which improves the soft gain compression of the power amplifier by 5.1dB to provide an overall more linear AM-AM profile allowing reduced power back-off for modulation schemes with a high peak-to-average ratio. The proposed D-band transmitter consumes 255mW and occupies 2000 × 1500 um of silicon area. The proposed transmitter delivers a 0.4 dBm EIRP and a saturated power on chip of 13.2 dBm. The transmitter has a peak PAE of 8.2% with power delivered to the antenna and a peak PAE of 0.4% when considering radiated power.

Millimeter-Wave-based radar has gained attention in recent years for automotive and object detection applications. Several new applications are also emerging which employ mm-Wave radar techniques to construct short range mm-Wave 3D imaging systems for security screening and biomedical applications. At present, these types of 3D mm-Wave imagers have only been demonstrated in lll-V technology, as CMOS-based radar suffers several range and resolution limitations due to limited output power and linearity.Most CMOS mm-Wave radar systems used in automotive applications are based on Frequency-Modulated Continuous-Wave (FMCW) ranging techniques in which the carrier is swept to produce a frequency offset at the receiver output proportional to the round-trip distance between the radar and target. While FMCW is an excellent approach for accurate ranging, its implementation becomes particularly difficult at high frequencies as the resolution is heavily dependent on sweep linearity and the high RF front-end performance required to support the wideband swept carrier. For 3D mm-Wave imaging applications, this high operating frequency is indispensable as the attainable spatial (XY) resolution is fundamentally limited by the wavelength of the imaging system. Higher frequency also helps relax focusing lens requirements, as the optical diffraction limit is set by the ratio of the radar wavelength over the lens aperture size.