GaN is an interesting material for power application but requires increasing process reliability. In this work, Au/ Ni ohmic contacts on p-type GaN are studied over a complete process flow representative of a real die fabrication. The impact of passivation and refill layers on the contact quality are investigated. First results reveal that Si based passivation degrades the ohmic behavior whereas Parylene passivation allows to keep the contact integrity. The addition of Al refill layer has only a slight impact on the best I-V characteristics. After a complete stack process, composed of two passivation and two refill layers, only fully Parylene passivated samples lead to an ohmic contact with a quasi-linear I-V response and a corresponding average SCR value of 0.96-2.79 x 10-3 Omega cm2.

In this work, non-recessed and Au-free low resistance Ohmic contacts are investigated on AlGaN/GaN on silicon. Based on Ti/Al bilayers, Circular TLM are fabricated and contact values are extracted varying different parameters such as single and combined annealing temperatures and surface treatment. Alloy formation upon annealing has been monitored by XRD. The results indicated that two phases, Ti3AlN and cubic TiAl3, have been formed upon annealing. Furthermore, the increase of Al thickness (up to 240 nm) resulted in a tetragonal TiAl3 phase formation, with a contact resistance degradation. Finally, we have shown that a low contact resistance (1 Ω mm) is achievable after clean 1 (Caro's + SC1 + HF) and upon annealing at 500 °C for 3 min and 800 °C for 30 s when using 70 nm and 180 nm of Ti and Al, respectively. In this case, the presence of an additional Ti3AlN (111) phase has been identified and is certainly the origin of the high quality of the Ohmic contact.

In this work, non-recessed and Au-free low resistance Ohmic contacts are investigated on AlGaN/GaN on silicon. Based on Ti/Al bilayers, Circular TLM are fabricated and contact values are extracted varying different parameters such as single and combined annealing temperatures and surface treatment. Alloy formation upon annealing has been monitored by XRD. The results indicated that two phases, Ti3AlN and cubic TiAl3, have been formed upon annealing. Furthermore, the increase of Al thickness (up to 240nm) resulted in a tetragonal TiAl3 phase formation, with a contact resistance degradation. Finally, we have shown that a low contact resistance (1Ωmm) is achievable after clean 1 (Caro's + SC1 + HF) and upon annealing at 500°C for 3min and 800°C for 30s when using 70nm and 180nm of Ti and Al, respectively. In this case, the presence of an additional Ti3AlN (111) phase has been identified and is certainly the origin of the high quality of the Ohmic contact.

La0.7Sr0.3MnO3 manganite thin films are interesting since they have a fully spin-polarized conduction band at room temperature and this opens the way for applications in electronics. An important issue is their magnetic heterogeneity, which is very difficult to detect. We address here the heterogeneity detection issue in two epitaxial LSMO thin films (57 nm and 90 nm thick) on Si substrate fabricated by reactive molecular beam epitaxy (MBE) deposition. Combining three complementary analytic techniques, we measured structural and magnetic behavior of these films. The high frequency ferromagnetic resonance behavior observed in these two LSMO samples put in evidence a standard dynamic behaviour in the case of the homogeneous material and an uncommon multi-mode behavior in the heterogeneous bi-layered film. The multi-mode behavior can be attributed to the presence of two magnetic sub-layers inside the LSMO film. Indeed, transmission electron microscopy observations and neutron reflectivity measurements are essential to give a microscopic description of the structure and intrinsic magnetic homo/heterogeneity of the composite film.

Local p-type doping in GaN is a key issue for device development but it remains a challenge to be achieved. In this work, we studied the activation of Mg implanted in the GaN. Multi-energy implantations were performed to achieve a "box-like" profile. SIMS measurements showed unexpected deep Mg profile due to defect-assisted channeling in the GaN. In addition, a high-density defect region induced by the implantation was evidenced by TEM characterization. To protect the GaN surface prior to high temperature annealing, an AlN cap-layer was deposited by reactive sputtering followed by SiOx deposition leading to a double cap-layer. Afterwards, the capped samples were RTA-annealed at high temperatures for several minutes under nitrogen. Two types of annealing processes were applied: a monocycle and a multicycle annealing. After annealing, the double cap-layer was etched using chemical solutions. AFM characterizations, after annealing and cap-layer etching, demonstrated that a GaN surface with similar roughness to as-grown samples and pit-free can be achieved after both monocycle and multicycle annealing steps. However, an AlGaN layer at the AlN/GaN interface is observed by ToF-SIMS and remained after the etching of the AlN layer. Finally, Schottky diodes were processed on the unimplanted and annealed samples, evidencing a double barrier, while P/N junction diodes are still being processed on the implanted and annealed samples. (C) 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim

This paper suggests the evaluation of morphological parameters of porous silicon layers (PSL) using spectroscopic ellipsometry from UV to mid-infrared optical range. PSL were prepared by electrochemical etching of monocrystalline silicon wafers in hydrofluoric acid-based electrolyte. Measuring with an optical and an infrared ellipsometer with a wide spectral range permits an accurate characterization of PSL properties from the top surface to the bottom of the layer with thicknesses from several hundred nanometers up to a few tens of micrometers. Several different optical models for ellipsometric evaluations were developed to determine the thickness, the average porosity, the in-depth porosity gradient, the oxidation level and the surface roughness of the PSL. Porosity was modeled with multiple effective medium layers by varying ratio of crystalline silicon, void and oxidized silicon wherever needed. Thin PSL (<5 mu m) show no impact of current density on porosity and thickness. However, evaluation of thick PSL (20-50 mu m) highlights the in-depth porosity gradient. Thickness values were also cross-checked with electron microscopy confirming the proposed ellipsometric models. Additionally, different oxidation techniques have also been compared in terms of oxidation level and void content. Volume expansion during PSL oxidation follows exactly the same behavior as that during the oxidation of planar silicon wafers. (C) 2016 Elsevier Inc. All rights reserved.

Due to their fabrication simplicity, fully compatible with low-cost large-area device assembly strategies, source-gated transistors (SGTs) have received significant research attention in the area of high-performance electronics over large area low-cost substrates. While usually based on either amorphous or polycrystalline silicon (α-Si and poly-Si, respectively) thin-film technologies, the present work demonstrate the assembly of SGTs based on single-crystalline ZnO sheet (ZS) with asymmetric ohmic drain and Schottky source contacts. Electrical transport studies of the fabricated devices show excellent field-effect transport behaviour with abrupt drain current saturation (IDS(SAT)) at low drain voltages well below 2 V, even at very large gate voltages. The performance of a ZS based SGT is compared with a similar device with ohmic source contacts. The ZS SGT is found to exhibit much higher intrinsic gain, comparable on/off ratio and low off currents in the sub-picoamp range. This approach of device assembly may form the technological basis for highly efficient low-power analog and digital electronics using ZnO and/or other semiconducting nanomaterial.

Two-dimensional imaging of dopant profiles for n and p-type regions are relevant for the development of new power semiconductors, especially for gallium nitride (GaN) for which classical profiling techniques are not adapted. This is a challenging task since it needs a technique with simultaneously good sensitivity, high spatial resolution and high dopant gradient resolution. To face these challenges, scanning capacitance microscopy combined with Atomic Force Microscopy is a good candidate, presenting reproducible results, as demonstrated in literature. In this work, we attempt to distinguish reliably and qualitatively the various doping concentrations and type at p–n and unipolar junctions. For both p–n and unipolar junctions three kinds of samples were prepared and measured separately. The space-charge region of the p–n metallurgical junction, giving rise to different contrasts under SCM imaging, is clearly observed, enlightening the interest of the SCM technique.

In the present work, we report the high performance of zinc oxide (ZnO) nanosheet (NS) based source-gated transistors (SGTs) with asymmetric Schottky source and ohmic drain contacts: low saturation drain-source voltages (~2V) in the output scans (even at high gate voltages), high current on/off ratio (>107) and low off-currents (0.1pA). For a deeper understanding of the device mechanism and charge transport at metal–semiconductor contact interface, temperature dependent current–voltage studies have been performed. They revealed that the device operation can be ascribed to 3 main processes: i) the reverse biased Schottky source contact, which essentially controls charge carrier injection in to the NS channel, ii) effective manipulation of the source barrier by the gate field and iii) modulation of the depletion region beneath the source contact. These results are likely to improve the future generations of the ZnO based SGTs which offer several advantages for thin-film transistor design, including low power dissipation, small signal amplification, and as active load for the electronic circuits.

P/N junctions have been fabricated with N + commercial 4H-SiC substrate on which Vapor-Liquid-Solid (VLS) selective epitaxy was used to create a localized p-type doping. The influence of the carrier gas nature (argon or hydrogen) has been investigated in terms of quality of the growth morphology, deposit thickness and electrical behavior of the P/N junction. Distinct results have been observed with a clear improvement when using VLS selective epitaxy under hydrogen.

Gallium nitride (GaN) is generally considered a good candidate for power electronic devices such as Schottky barrier diodes (SBDs). Nevertheless, GaN has a strong sensitivity to high temperature treatments and a cap-layer is mandatory to protect the material surface during annealing at high temperature such as post-implantation treatments. In this work, an oxidized gallium nitride layer (GaOxNy) was generated with Oxford PECVD equipment using a N2O plasma treatment to protect the GaN surface during a rapid thermal annealing (RTA), in the range of 1000 °C–1150 °C for a few minutes. Before annealing, c-TLM patterns were processed on the GaOxNy/GaN sample to characterize its sheet resistance. After the N2O plasma treatment, the sample exhibited lower sheet resistance, indicating a better n-type conduction of the GaOxNy layer due to an excess of free carriers, compared to the as-grown GaN layer. The GaOxNy/GaN surface was then annealed at 1150 °C for 3 min and observed through AFM imaging. The surface exhibited a good quality with a low roughness, nevertheless, a low density of small hexagonal pits appeared after annealing. Finally, studies to determine an efficient etching process of the GaOxNy cap-layer were conducted using both chemical and physical approaches. We observed that efficient etching of the layer was achieved using a heated hydrofluoridric acid (HF 25%) solution. To conclude, GaOxNy has proved to be an efficient cap-layer for GaN protection at high temperature.

Efficient edge terminations are fundamental for power electronic devices. High resistive edge termination technique obtained by ion implantation is a possible solution for GaN Schottky barrier diodes (SBD), but may induce defects detrimental to the devices. In this work, two sets of GaN SBDs, with or without a high resistive guard ring edge termination, were investigated by deep levels transient spectroscopy (DLTS). The corresponding DLTS spectra of devices with guard ring were compared to those of as‐fabricated devices (without). Four deep traps at 0.13, 0.26, 0.35, and 0.51 eV were observed below the conduction band in as‐fabricated structures while the ones with guard ring exhibit two additional levels at 0.47 and 0.80 eV and a strong enhancement in DLTS peaks magnitude. Further investigations showed that the additional traps detected in SBD devices with guard ring were consistent with ion implantation‐induced damages. These observations highlight the impact of high resistive edge termination technique on our devices and raise the need of optimization of such crucial structure for the improvement of GaN‐based Schottky barrier diode.

The production of large quantities of single crystalline semiconducting ZnO nanowires (NWs) at low cost can offer practical solutions to realizing several novel electronic/optoelectronic and sensor applications on an industrial scale. The present work demonstrates high-density single crystalline NWs synthesized by a multiple cycle hydrothermal process at ∼100 °C. The high carrier concentration in such ZnO NWs is greatly suppressed by a simple low cost thermal annealing step in ambient air at ∼450 °C. Single ZnO NW FETs incorporating these modified NWs are characterized, revealing strong metal work function-dependent charge transport, unobtainable with as-grown hydrothermal ZnO NWs. Single ZnO NW FETs with Al as source and drain (s/d) contacts show excellent performance metrics, including low off-state currents (fA range), high on/off ratio (105–107), steep subthreshold slope (<600 mV/dec) and excellent field-effect carrier mobility (5–11 cm2/V-s). Modified ZnO NWs with platinum s/d contacts demonstrate excellent Schottky transport characteristics, markedly different from a reference ZnO NW device with Al contacts. This included abrupt reverse bias current–voltage saturation characteristics and positive temperature coefficient (∼0.18 eV to 0.13 eV). This work is envisaged to benefit many areas of hydrothermal ZnO NW research, such as NW FETs, piezoelectric energy recovery, piezotronics and Schottky diodes.

The present work investigates charge carrier transport in back-gated field-effect transistors based on ZnO sheets (BG ZS-FETs). The ZSs used in this work have been synthesized via the catalytic-assisted vapor-liquid-solid process inside a horizontal quartz tube furnace at around 950 degrees C. The BG ZS-FETs were constructed as bottom-gate top-contact structures using suspended and nonsuspended ZS as the active channel material. Assessment of key device performance metrics revealed excellent n-channel behavior with low off-state current in the femtoamp range, high onstate current (similar to 2 mu A/mu m), high on-to-off current ratio (>10(7)), a steep sub-threshold swing of around 190 mV/dec, and field-effect carrier mobility of around 60 cm(2)/Vs. Temperature dependent charge transport studies reveal excessive mobility degradation in the non-suspended device while the same parameter in the suspended case appeared fairly stable. The present work is envisaged to benefit ongoing research towards the development of high performance ZS-based thin-film transistors. (C) 2015 AIP Publishing LLC.

We demonstrate single crystalline ZnO nanowire (NW) production using hydrothermal process. Single NW field-effect transistors (FETs) and functional piezoelectric nanogenerators (NGs) are demonstrated by thermal annealing of the NWs in air at ~450 °C.

Critical issues need to be overcome to produce high performance Schottky diodes on gallium nitride (GaN). To activate dopant, high temperature thermal treatments are required but damage GaN surface where hexagonal pits appear and prevent any device processing. In this paper, we investigated the efficiency of cap-layers on GaN during thermal treatments to avoid degradation. Aluminum nitride (AIN) and silicon oxide (SiOx) were grown on GaN by direct current reactive magnetron sputtering and plasma-enhanced chemical vapor deposition, respectively. AIN growth parameters were studied to understand their effect on the grown layers and their protection efficiency. Focused ion beam was used to measure AIN layer thickness. Crystalline quality and exact composition were verified using X-ray diffraction and energy dispersive X-ray spectroscopy. Two types of rapid thermal annealing at high temperatures were investigated. Surface roughness and pits density were evaluated using atomic force microscopy and scanning electron microscopy. Cap-layers wet etching was processed in H3PO4 at 120 degrees C for AIN and in HF (10%) for SiOx. This work reveals effective protection of GaN during thermal treatments at temperatures as high as 1150 degrees C. Low surface roughness was obtained. Furthermore, no hexagonal pit was observed on the surface. (C) 2015 Elsevier B.V. All rights reserved.

Using vertically grown hydrothermal ZnO nanowires, we demonstrate the assembly of fully functional piezoelectric energy harvesters on plastics substrates. A seedless hydrothermal process is employed for the growth of single crystalline vertically orientated ZnO NWs at around 100oC. Flexible NG are assembled using ∼7μm thick PDMS polymer matrix on a 3x3cm substrate. A representative device with an active area of 4cm2 is characterised revealing average output voltage generation of ∼22mV (±1.2) and -32mV (±0.16) in the positive and negative cycles after 3-4mm periodic deflection at 20Hz. A power density of ∼288nW/cm3 is estimated for the device. It is envisaged that such energy scavengers may find potential applications targeting self-powered systems, sensors and on-body charging of electronics.

Single-crystalline silicon wafers covered with sacrificial oxide layer and epitaxially grown gallium nitride layers were implanted with high-fluence helium ions (2–6×1016cm−2) at energies of 20–30keV. Thermal annealings at 650–1000°C, 1h were performed on the Si samples and rapid thermal annealings at 600–1000°C, 120s under N2 were performed on the GaN samples. The as-implanted samples and the near-surface cavity distributions of the annealed samples were investigated with variable angle spectroscopic ellipsometry. In-depth defect profiles and cavity profiles can be best described with multiple independent effective medium sublayers of varying ratio of single-crystal/void. The number of sublayers was chosen to maximize the fit quality without a high parameter cross-correlation. The dependence of the implantation fluence, oxide layer thickness and annealing temperature on the cavity distribution was separately investigated. The ellipsometric fitted distributions were compared and cross-checked with analyses of transmission electron micrographs where the average surface cavity was determined sublayer by sublayer. The in-depth profiles were also compared with simulations of He and vacancy distributions.