A fast, low noise, limited power, radiation-hard front-end chip was developed for reading out the Atlas Pixel Silicon Detector. As in the past prototypes, every chip is used to digitize and read out charge and time information from hits on each one of its 2880 inputs. The basic column readout architecture idea was adopted and modified in order to allow a safe transition to quarter micron technology and overcome any possible situation where single point defects and charge deposited by heavy ions in the silicon could have lead to unpredicted forbidden states. Moreover, the smaller feature sizes and the higher speed of these processes allowed us to enhance the design of the basic blocks and adopt a fail safe, design for testability approach.

Prototype sensors for the ATLAS silicon pixel detector have been electrically characterized. The current and voltage characteristics, charge-collection efficiencies, and resolutions have been examined. Devices were fabricated on oxygenated and standard detector-grade silicon wafers. Results from prototypes which examine p-stop and standard and moderated p-spray isolation are presented for a variety of geometrical options. Some of the comparisons relate unirradiated sensors with those that have received fluences relevant to LHC operation.

A new analog pixel front-end cell has been developed for the ATLAS detector at the future Large Hadron Collider (LHC) at the European Laboratory for Particle Physics (CERN). This analog cell has been submitted in two commercial 0.25 /spl mu/m CMOS processes (in an analog test chip format), using special layout techniques for radiation hardness purposes. It is composed of two cascaded amplifiers followed by a fast discriminator featuring a detection threshold within the range of 1000 to 10000 electrons. The first preamplifier has the principal role of providing a large bandwidth, low input impedance, and fast rise time in order to enhance the time-walk and crosstalk performance, whereas the second fully differential amplifier is aimed at delivering a sufficiently high-voltage gain for optimum comparison. A new do feedback concept renders the cell tolerant of sensor leakage current up to 300 nA and provides monitoring of this current. Two 5-bit digital-to-analog converters tolerant to single-event upset have been implemented for threshold and recovery-time pixel-to-pixel matching purposes. Special attention has been paid to the power-supply rejection ratio to minimize sensitivity to pickup. The complete cell dissipates 30 /spl mu/W, occupies an area of 50/spl times/90 /spl mu/m/sup 2/ and is operated with a single 1.6-V power supply. Measurements of two test chips are presented.

Prototype sensors for the ATLAS silicon pixel detector have been developed. The design of the sensors is guided by the need to operate them in the severe LHC radiation environment at up to several hundred volts while maintaining a good signal-to-noise ratio, small cell size, and minimal multiple scattering. The ability to be operated under full bias for electrical characterization prior to attachment of the readout integrated circuit electronics is also desired.

The demanding requirements for pixel readout electronics for high-energy physics experiments and biomedical applications are reviewed. Some examples of the measured analog performance of prototype chips are given. The readout architectures of the Pixel Readout fdr the ATlas Experiment (PIRATE) chip suited for LHC experiments and of the Multi Picture Element Counter (MPEC) counting chip targeted for biomedical applications are presented. First results with complete chip-sensor assemblies are also shown. (C) 2000 Elsevier Science B.V. All rights reserved.

The MEPHISTO chip uses a novel binary architecture to achieve a high speed readout for multichannel detectors, like silicon strip detectors or MSGCs. The architecture is an alternative to existing designs with raw data pipelines as are commonly used in particle physics applications. The chip receives 128 digital input signals from an analog front end chip at a rate of up to 80 MHz. The hit pattern is sparsified in real time and only the addresses and interaction times of hits are stored temporarily in FIFOs. Multiple hits per event are possible. A trigger selects interesting events for readout. All other hits are automatically discarded. Untriggered readout at high rates is also possible. The occupied chip area depends on the average data rate which can be very small in many applications. Very compact designs with up to ten times less first level storage can therefore be realized.

Pixel detectors with a high granularity and a very large number of sensitive elements (cells) are a very recent development used for high precision particle detection. At the Large Hadron Collider LHC at CERN (Geneva) a pixel detector with 1.4 * 10(8) individual pixel cells is developed for the ATLAS detector. The concept is a hybrid detector consisting of a pixel sensor connected to a pixel electronics chip by bump and flip chip technology in one-to-one cell correspondence. The development and prototype results of the pixel front end chip are presented together with the physical and technical requirements to be met at LHC. Lab measurements are reported.

We present a VLSI CMOS-mixed analog-digital circuit for high-rate pixel X-ray imaging applications. It consists of 32 channels at 80 mu m pitch. The total die size is 3.7 x 14 mm(2). Each channel features: a low-noise charge preamplifier, a CR-RC shaper, a buffer, a threshold discriminator and a 16-bit binary counter. The readout is done serially on a tri-state buffer. The main parameters of the analog part are: shaping time of 850 ns at 5 pF input capacitance, gain of 180 mV/fC, ENC (e(-) rms) = 60 + 17 C-d (pF) and a power consumption of 3.8 W/channel. The counting rate is limited by the analog part to around 100 kHz/channel for 1 fC charge pulses. Due to the parallelism of the circuit, photon rate in the order of 1 GHz/cm(2) can be measured for a pixel size of the order of 200 x 200 mu m(2).The parameters of the circuit were optimised for the Syrmep experiment, an R&D project in digital mammography. The circuit was produced in 1.2 mu m CMOS technology by AMS (Austria). Characterisation of the circuit, as well as first-imaging results of the circuit connected to microstrips or pixel detectors are presented. They show the circuit works according to specification and can be used for imaging applications.

In this paper we present the design and first experimental results of a VLSI mixed analog-digital 1.2 microns CMOS circuit (CASTOR) for multichannel radiation detectors applications demanding low noise amplification and counting of radiation pulses. This circuit is meant to be connected to pixel-like detectors. Imaging can be obtained by counting the number of hits in each pixel during a user-controlled exposure time.Each channel of the circuit features an analog and a digital part. In the former one, a charge preamplifier is followed by a CR-RC shaper with an output buffer and a threshold discriminator. In the digital part, a 16-bit counter is present together with some control logic. The readout of the counters is done serially on a common tri-state output. Daisy-chaining is possible.A 4-channel prototype has been built. This prototype has been optimised for use in the digital radiography Syrmep experiment at the Elettra synchrotron machine in Trieste (Italy): its main design parameters are: shaping time of about 850 ns, gain of 190 mV/fC and ENC (e(-) rms) = 60 + 17 C (pF). The counting rate per channel, limited by the analog part, can be as high as about 200 kHz.Characterisation of the circuit and first tests with silicon microstrip detectors are presented. They show the circuit works according to design specification and can be used for imaging applications.