In this paper, the most upgraded 4nm (SF4X) ensuring HPC application was successfully demonstrated. Key features are (1) Significant performance +10% boosting with Power -23% reduction via advanced SD stress engineering, Transistor level DTCO (T-DTCO) and MOL scheme, (2) New HPC options: Ultra-Low-Vt device (ULVT), high speed SRAM and high Vdd operation guarantee with a newly developed MOL scheme. SF4X enhancement has been proved by a product to bring CPU Vmin reduction -60mV / IDDQ -10% variation reduction together with improved SRAM process margin. Moreover, to secure high Vdd operation, Contact-Gate breakdown voltage is improved by $\gt 1\mathrm{V}$ without Performance degradation. This SF4X technology provides a tremendous performance benefits for various applications in a wide operation range.

In this paper, a leading edge High performance 4nm FinFET Platform (4LPE) is demonstrated, featuring a novel advanced Transistor level DTCO (T-DTCO) in Middle-of-Line/Back-End-of-Line and careful process optimization, which enables dual-CPP/HP-HD standard cell with Gate contact-over-RX scheme. Compared to 5nm Platform (5LPE), Performance +7~10% and Power -12% gain are successfully obtained in both typical and low Vdd, as well as a flat layout dependence. 4LPE enhancement is accomplished by design-manufacturing favorable approaches. Moreover, newly adapted SRAM Ultra High-Density cell (UHD), Product IDDQ variation control and reliability verifications were completed for the technology delivery.

We demonstrate 28-nm embedded MRAM (eMRAM) macro for non-volatile RAM (nvRAM) applications, featuring macro density of 12.5 Mb/mm2, write speed < 100 ns, 10-yrs retention at 125 °C, and endurance > 1E9 cycles. This is the smallest 28-nm nvRAM-type eMRAM macro reported to date and provides ~2× area saving compared to SRAM while providing native non-volatility and low stand-by power.

In this paper, we demonstrate state of the art 5nm technology (5LPE) having co-optimization process for Dual CPP (Critical Poly-Pitch) technology to maximize Product Power-Performance-Area by separating both high speed and low power blocks. As a result, 5LPE successfully has 10% speed gain or 20% power gain and 0.75x logic area over our previous 7nm technology [1] with more advanced FinFET technology having EUV process and design optimization.

CMOS Image Sensor(CIS) products need higher voltage device and better analog characteristics than conventional SOC & Logic products. This work presents newly developed 14nm FinFET process with 2.xV high voltage FinFET device characteristics showing excellent analog and low power digital characteristics comparing to 28nm planar process. Gm is improved by 30% and 67% in FinFET process for NMOS and PMOS, respectively. Rout characteristics increased by 40 times and 6 times over 28nm planar process. Interface state density(Nit) improved by more than 40% and flicker noise characteristics also improved by 64% and 42% for NMOS and PMOS, respectively. Digital logic Transistor ion-ioff performance improved by by 32% and by 211% for NMOS and PMOS, respectively compared to 28nm planar device and the chip power consumption of digital logic functional block reduced by 34% in real Si of 12M pixel product. 14nm FinFET process expected to improve power consumption by 42% in 144M pixel density.

We demonstrate, for the first time, 28-nm embedded STT-MRAM operating at full industrial temperature range (-40 similar to 125 degrees C) with >1E+6 endurance and >10 year retention for high speed MCU/IoT application. Robust cell operation is also demonstrated after solder reflow (260 degrees C, 90 second) and during external magnetic disturbance (550-Oe under writing). It is built on 28-nm FDSOI technology in modular format for IP reuse and has great potential to serve wide variety of applications such as IoT, and high performance MCU.

An O-band DFB laser heterogeneously integrated on bulk-silicon platform is presented. A high wall plug efficiency of over 8% up to 70°C is achieved due to efficient heat dissipation from III/V active region to silicon platform. The single-mode operation is maintained in a wide current range with side-mode suppression ratio over 45dB. This result completes the optical device library suite for the bulk-silicon platform used in most semiconductor products.

The huge amount of information has a great impact on our daily lives, which can be filled with comfort, convenience, and safety by using and analyzing the so-called big data. It is noteworthy that we can store, share, and utilize the huge amount of data with the aid of silicon (Si) technology; the novel Si technologies will be deployed to continuously enrich the data-driven world of the future. This chapter reviews the evolution and prospects for the future Si technologies. The Si-based memory and logic technologies have been successfully scaled down to 1X nm node. From the device point of view, all of the Si devices face no fundamental physical limitations down to sub-10nm nodes. Practically, fabrication cost and manufacturability are of increasing concern. Patterning difficulties, as well as tight overlay and uniformity tolerances, will increase fabrication costs. Along with individual technology evolution, the convergence of various technologies will generate new areas of functional diversification.

We present photonics technology based on a bulk-Si substrate for cost-sensitive dynamic random-access memory (DRAM) optical interface application. We summarize the progress on passive and active photonic devices using a local-crystallized Si waveguide fabricated by solid phase epitaxy or laser-induced epitaxial growth on bulk-Si substrate. The process of integration of a photonic integrated circuit (IC) with an electronic IC is demonstrated using a 65 nm DRAM periphery process on 300 mm wafers to prove the possibility of seamless integration with various complementary metal-oxide-semiconductor devices. Using the bulk-Si photonic devices, we show the feasibility of high-speed multidrop interface: the Mach–Zehnder interferometer modulators and commercial photodetectors are used to demonstrate four-drop link operation at 10 Gb/s, and the transceiver chips with photonic die and electronic die work for the DDR3 DRAM interface at 1.6 Gb/s under a 1∶4 multidrop configuration.

Needs for the performance improvement of memory subsystem in big data and clouding computing era begin to open new markets for emerging memories such as phase change memory, spin-torque-transfer magnetic memory, and metal oxide memory. To fulfill these needs, a cost-effective and high-speed phase change memory cell scheme was introduced at 19nm technology node, which is directly scalable down to 1y or 1z nm nodes and can be extendable to stacked array for higher density. Here, key technologies such as self-aligned cell patterning and vertical poly-Si diode switch on metal word line were adopted. In addition, damascene Ge-Sb-Te technologies were optimized to improve programming speed and to show excellent cell performances.

We designed and fabricated a 1.3-um hybrid vertical Resonant-Cavity Light-Emitting Diode for optical interconnect by using direct III-V wafer bonding on silicon on insulator (SOI). The device included InP based front distributed Bragg reflector (DBR), InGaAlAs based active layer, and SOI-based high-contrast-grating (HCG) as a back reflector. 42-uW continuous wave optical power was achieved at 20mA at room temperature.

Phase-change RAM, magnetic RAM, and resistive RAM offer strong scalability, speed, and power consumption advantages over conventional capacitance-based memory. Recent work shows the feasibility of mass producing these new devices and their suitability for next-generation technology.

In this paper, current-voltage-temperature (I-V-T) characteristics of vertical diodes realized by different selective epitaxial growth techniques have been investigated. Diodes by the batch-type cyclic SEG process at low temperature have shown eligible performances for vertical switches, including ideality factor of 1.08, off-current of 1.0×10-12 A and on/off-ratio of 2.4×108. The optimization of crystallographic defects and series resistance is expected to be the most critical for the performances of vertical diodes for next generation memories.

The cell failures after cycling endurance in phase-change random access memory (PRAM) have been classified into three groups, which have been analyzed by transmission electron microscopy (TEM). Both stuck reset of the set state (D0) and stuck set of the reset state (D1) are due to a void created inside GeSbTe (GST) film or thereby lowering density of GST film. The decrease of the both set and reset resistances that leads to the tails from the reset distribution are induced from the Sb increase with cycles.

This paper discussed the key reliability issues for manufacturing high density phase change memory (PRAM). There are its own unique phenomena, such as resistance fluctuation, structural relaxation and crystallization, which are closely correlated with the device reliability characteristics, including data retention, cycling endurance, and write disturbance. Optimizing material composition and controlling doping concentration and minimizing variability of physical dimensions can improve the reliability issues. Above all, isotropic dimension scaling along with writing current scaling is essential for continuing scaling down below 20 nm node.