The discovery of ferroelectricity in hafnia-based thin films has paved the way for their integration into non-volatile memory technologies, offering compatibility with CMOS processes and the potential for aggressive scaling. One significant aspect impacting the reliability and performance of ferroelectric Hf0.5Zr0.5O2 (HZO) capacitors is the oxygen vacancy (VO) concentration, which influences endurance, retention, and polarization stability. This study investigates the VO concentration profile for the woken-up state (10(4) cycles) in HZO-based ferroelectric capacitors (FeCAPs) in different polarization states (P. and P.). The VO distribution is quantified using Hard X-ray photoemission spectroscopy (HAXPES), using incident photon energies from 3 to 9 keV to calculate the VO concentration profile across the HZO layer non-destructively. Results indicate that VO accumulates near the top TiN/HZO interface for the P. state, while they drift toward the bottom HZO/TiN interface for the P. state under the effect of the internal polarization field. This polarization-dependent VO distribution correlates with voltage and field offsets observed in electrical measurements, providing insights into defect mobility that can inform FeRAM device optimization. Our results show that the polarization behavior, i.e. the alignment and stability of electric dipoles within the HZO layer, strongly correlates with the distribution of VO, which plays a crucial role in enhancing the reliability and performance of ferroelectric memory devices. These findings enhance our understanding of the coupling between defect chemistry and ferroelectric properties in HZO, supporting the engineering of high-performance, CMOS-compatible ferroelectric memory technologies.
In this study, various charge trapping mechanisms and their effects on the endurance of n- and p-type HfO 2 -based FeFETs, integrated within GlobalFoundries 28 nm bulk high-k metal gate (HKMG) technology are examined. The device's endurance is impaired due to pronounced interface degradation and charge injection into the Metal-Ferroelectric-Insulator-Semiconductor (MFIS) gate stack caused by the high interfacial field stress. By analyzing threshold voltage shifts under both bipolar and unipolar cycling, as well as bipolar endurance cycling for “non-ferroelectric” samples with diminishing remanent polarization levels, the study reveals the critical role of polarization switching in endurance degradation. The findings highlight the deterioration of the gate stack and specifically of the interface of FeFETs upon bipolar cycling which strongly affects the electrical characteristics and causes increased electron trapping in n-type-FeFETs and hole trapping in p-type FeFETs. This effect is particularly pronounced for each device's low threshold-voltage (LVT) state and is intensified by polarization switching. The study's results contribute to a deeper understanding of the charge trapping phenomena in HfO 2 -based FeFETs and their impact on device performance and reliability.
Training neural networks for large-scale applications such as pattern extraction and speech processing are time and resource-intensive. The utilization of crossbar architectures designed with non-volatile memories (NVMs), such as Resistive RAMs (RRAMs), facilitates in-memory computing and can accelerate the training process, including forward and backward passes. To accelerate the weight update process, Resistive Processing Units (RPUs) are incorporated at the crosspoint in arrays. However, RRAMs can only represent a limited number of conductance levels, which affects the accuracy of weight gradient calculation, thus affecting the accuracy of the overall network. In the literature, a requirement of 1000 conductance levels in memristors for efficient training, especially weight update operation using RPU, is shown. In prior works, to achieve more conductance levels, multiple memristors are used for a single-bit cell. However, for a linear increase in levels, a linear increase in hardware is needed to be employed. In this work, we propose an area-efficient multi-RRAM bit cell design to attain the required number (1000) of conductance levels and model the bit cell to quantitatively show > 86% accuracy using a hardware-efficient scheme. The RRAMs are connected in a weighted conductance manner, increasing conductance exponentially for a linear increase in hardware. We show a similar to 33x reduction in RRAM devices and similar to 5.6x reduction in transistor count per bit cell with our proposed design to achieve 1000 levels.
Nonvolatile memories (NVMs) have emerged as promising candidates for efficient analog compute-in-memory (CIM). However, high power consumption and large variations in NVMs are key factors hindering the performance of analog computing. In this work, we demonstrated an 8Kb 1T-1R CIM macro-array utilizing spin-orbit torque (SOT) magnetic random-access memory (MRAM). The SOT-MRAM features high cell resistance at parallel magnetization configuration (RP) of 2MO and low resistance standard variation-to-average ratio of 4.2% The CIM array achieves 10ns write speed and no endurance failures up to 1010 write cycles. Moreover, the linear analog multiply-accumulate (MAC) output maintains a sufficiently high accuracy, making it well-suited for binary neural network (BNN) applications in edge devices.
The development of scalable and CMOS-compatible cryogenic quantum processors necessitates embedded non-volatile random-access memory to support computation while controlling heat generation under cryogenic conditions. However, conventional memory technologies based on magnetoresistive and resistive effects encounter significant self-heating issues. Consequently, hafnium oxide-based ferroelectric field-effect transistors emerge as a promising alternative. In this study, we first evaluated their endurance across various temperatures, including cryogenic temperatures down to 2 K. We then characterized their temperature-dependent data retention behaviour at each temperature, observing and discussing a notably long electron detrapping time at 2K. Additionally, we analyzed the flicker noise of the transistors in two ferroelectric polarization states.
FRAM technology development has seen a significant revival over the last decade due to the discovery of ferroelectricity in hafnia (HfO2). The field has progressed in various areas and advancements for embedded FRAM, standalone DRAM-type FRAM as well as for stacked FRAM using multiple ferroelectric capacitors is described. Furthermore, opportunities for ferroelectric memory technology to surpass DRAM memory densities in the future are discussed. Finally, since any memory technology should operate below 1V to be compatible to advanced process nodes, latest achievements for reducing coercive voltages in hafnia are summarized.
With the continuous shrink of CMOS technology node, the traditional latch circuit suffers from high power consumption owing to the increase of the static leakage current and faces severe reliability issue induced by the single event upset (SEU) in the space environment. To address these issues, a novel Radiation-Hardened Non-Volatile Magnetic Latch Circuit (short for RHNVMLC) is proposed, which mainly consists of four components, i.e., the pre-charge module composed of four PMOS transistors, the SEU-Tolerant latch module composed of four cross-coupled NMOS Dual-input Approximate C-elements (NDAC), the backup and restore module composed of two magnetic tunnel junctions (MTJs) in complementary state to store one bit information with the read/write control circuits, and the shared module composed of two transmission gates (i.e., TG1 and TG2) and three inverters (i. e., INV1, INV2 and INV3). It has four work modes, i.e., the latch, backup, standby and restore modes. By using a physics-based STT-MTJ compact model and a commercial CMOS 40nm design kit, hybrid CMOS/MTJ simulations have been performed to demonstrate its functionality. Simulation results demonstrate that the proposed RHNVMLC not only ensures non-volatility but also provides full SEU tolerance.
Hafnium oxide-based ferroelectric (FE) field-effect transistors (FeFETs) show great promise for non-volatile memory (NVM) applications due to their scalability, fast switching, and low power demands. A recent advancement, the 1T1C FE Metal Field-Effect Transistor (FeMFET), combines a single transistor (1T) with a separate metal-FE-metal (MFM) capacitor (1C) in the back-end-of-line (BEoL)-an approach crucial for both FeMFET and 1T1C FE Random Access Memory (FRAM) cells. This study investigates the impact of annealing conditions, TiN top and bottom electrode, and various BEoL MFM stack configurations-including standard Hf0.5Zr0.5O2 (HZO), superlattices (SL), and co-doped aluminum-hafnium zirconium oxide (HZAO)-on device performance. Findings show that SL stacks improve remanent polarization (2Pr), while HZAO stacks reduce coercive field (2Ec) values, enabling lower switching voltages and enhancing thermal resilience against imprint-a critical feature for automotive applications. Additionally, using dedicated annealing treatments, rather than the standard thermal budget of the BEoL, and optimizing TiN electrodes significantly reduces device-to-device variability. These advances in BEoL MFM stack integration address key challenges in device variability, data retention, and energy efficiency.
In-memory computing (IMC) is a computing paradigm inspired by the brain, implemented on an interconnected network of computing (neurons) and reconfigurable memory (synapse) elements that can perform multiply and accumulate (MAC) operations in the memory, thereby improving latency and reduce power consumption, mitigating the von Neumann bottleneck. Resistive memory is an emerging technology that can act as computing and memory elements employed in crossbar arrays to offer intrinsic MAC functionality. The analog MAC output is quantized to digital values using ADC for further computations in different applications. Therefore, the accuracy of ADC is crucial. This paper examines the impact and constraints of RRAM parameters on neural network density (n), including conductance ratio (k), memory window (MW), and device variability (Ivar), by analyzing the limit on ADC sensitivity margin (SM). First, we identify the critical SM point in the MAC output. Next, at the device level, we experimentally show the impact of k and Ivar on MW, which essentially defines the SM of an ADC. MW decreases by 10x with 10x smaller k and 30% Ivar. At the array MAC (column output) level, for a given k the limit on n decreases. Further, we empirically investigated that the tolerance to device variability can be achieved by increasing k. The enhancement can be realized by amplifying the MAC output multiplier solution that has been demonstrated to improve the device limit and design space requirements.
This paper reviews a Dynamic Flash Memory (DFM) based on the FinFET and Surrounding Gate Transistor (SGT) architectures. Like DRAM, the refresh is required, but Fast Block Refresh improves the duty ratio. Analogous to Flash, three basic operations of “0” Erase, “1” Program, and Read are necessary, but the ability to carry out the “1” refresh without using sense amplifiers enables the read and write operations in the background, which results in a faster system.
High switching current and energy are major challenges yet to be overcome effectively in phase change memory for large scale industry-level production. Superlattice based interfacial phase change memory (iPCM) has shown great potential in recent years to provide reduced current density operation. In this work, we perform finite element method based computational study on GeTe/Ge 2 Sb 2 Te 5 iPCM pillar cell and analyze the device performance for different material and structural parameters. The simulation results predict ~12.5% reduction in RESET energy in iPCM compared to the conventional PCM. We obtain ~4.6x decrease in RESET current when the device is scaled down from 50 nm to 10 nm. Increase in the number of periods of the superlattice results in less RESET current required, which can be attributed to the better thermal confinement due to additional thermal boundary resistances at the increased number of interfaces.
It is important to obtain ferroelectric HfZrO x (HZO) films at low crystallization temperatures to ensure compatibility with low-temperature processes. This study investigates the origin of degradation in ferroelectric properties of ferroelectric films at low crystallization temperatures, by modifying the bottom electrodes and HZO thicknesses. The TiN/HZO/TiN and W/HZO/W stacks exhibit no or very weak ferroelectric properties at all HZO thicknesses evaluated at a crystallization temperature of 300 °C. However, W/HZO/Pt exhibits ferroelectric properties for most of the range of HZO thicknesses evaluated, and exhibits a sufficient switchable polarization (2P r ) value of 39.83 μC/cm 2 at a HZO thickness of 12 nm. It is expected that this may be attributed to an interfacial dead layer that suppresses the formation of the ferroelectric phase. The formation of interfacial dead layer is indirectly confirmed using the pulse-switching technique. As a result, the HZO film with the Pt electrode exhibits a large interfacial capacitance compared with that of TiN and W electrodes, implying that the formation of the interfacial dead layer is minimized. These results indicate that a low thermal budget for ferroelectric HZO devices can be achieved by selecting an appropriate fabrication process that minimizes the formation of an interfacial layer.
This paper proposes a Dynamic Flash Memory (DFM) (Sakui and Harada, 2020; 2021 [1], [2]) with double storage gates and one select gate based on FinFET and Surrounding Gate Transistor (SGT) (Takato et al., 1988 [3]) architectures. Like DRAM (Dennard, 1967 [4]), refresh is required, but fast block refresh improves the duty ratio. Analogous to Flash (Masuoka, 1981 [5]), three basic operations of “0” Erase, “1” Program, and Read are necessary, but the ability to carry out Read-While-Erase (RWE), and Program-While-Erase (PWE) operations in the background results in a faster system.
The influence of depolarization and its role in causing data retention failure in ferroelectric memories is investigated. Ferroelectric Hf 0.5 Zr 0.5 O 2 thin films 8 nm thick incorporated into a metal-ferroelectric-metal capacitor are fabricated and characterized with varying thicknesses of an Al 2 O 3 interfacial layer. The magnitude of the depolarization field is adjusted by controlling the thickness of the Al 2 O 3 layer. The initial polarization and the change in polarization with electric field cycling is strongly impacted by the insertion of Al 2 O 3 within the device stack. Transient polarization loss is shown to get worse with larger depolarization fields and data retention is evaluated up to 85 °C.
A novel True Random Number Generator circuit fabricated in a 130nm HfO2-based resistive RAM process is presented.The generation of the random bit stream is based on a specific programming sequence applied to a dedicated memory array.In the proposed programming scheme, the voltage applied to the cells of the memory array is fixed at the median SET voltage of the distribution, to program only a subset of the memory array, resulting in a stochastic distribution of cell resistance values.Some cells are switched in a low resistive state, while the remaining cells maintain their initial high resistance state.Resistance values are next converted into a bit stream and confronted to National Institute of Standards and Technology (NIST) test benchmarks.The generated random bit stream has successfully passed eleven NIST tests out of fifteen without any post-processing.
The feasibility of the QD-Flash concept, its fast write and erase times, is demonstrated together with storage times of 4 days at room temperature. The storage time of holes in (InGa)Sb QDs embedded in a (AlGa)P matrix can be extended by growth modifications to 10 y. Tunneling structures were recently demonstrated to solve the trade-off conflict between storage time and erase time. A QD-NVSRAM is suggested to become the first commercial application.
We have successfully developed, for the first time, a new memory test system for STT-MRAM at wafer-level where an electromagnet is combined with a memory test system and a 300 mm wafer prober. In the developed memory test system, an out-of-plane magnetic field up to ±800 mT can be applied on 10x10 mm2 in the 300 mm wafer with distribution of less than 2.5%. We demonstrated that the electromagnet can apply large enough magnetic field to evaluate magnetic immunity properties for STT-MRAM using 2Mb STT-MRAM; magnetic field dependence of pass-bit rate for “0”/“1” states, read/write shmoo, and “0”/“1” retention. All the properties can be explained by general theory for STT-MRAM. The developed memory test system with the electromagnet is a key testing tool for STT-MRAMs, which will contribute to increase efficiency of STT-MRAM testing as well as widening the application area of STT-MRAM sensitive to an external magnetic field.
This paper discusses the reliability challenges of 3D NAND flash memory and their impact on flash management for enterprise storage applications. Emphasis is given to the read voltage calibration and its critical role in achieving low errorrates and low latency read performance, as well as in enabling accurate block health estimation. We present experimental results that demonstrate the improvements in endurance, retention and read-disturb from different read voltage calibration schemes, and we address their requirements from a system perspective, i.e., the accuracy vs. complexity trade-off. We discuss the above aspects for state-of-the-art 3D TLC and QLC NAND flash memory.
Crossbar arrays of non-volatile memory (NVM) devices represent one possible path for implementing highly energy-efficient neuromorphic computing systems. For Deep Neural Networks (DNN), where information can be encoded as analog voltage and current levels, such arrays can represent matrices of synaptic weights, implementing the matrix-vector multiplication needed for algorithms such as backpropagation in a massively-parallel fashion. Previous research demonstrated a large-scale hardware-software implementation based on phase-change memories and analyzed the potential speed and power advantages over GPU-based training. In this proceeding we will discuss extensions of this work leveraging a different class of memory elements. Using the concept of jump-tables we simulate the impact of real conductance response of non-filamentary resistive devices based on Pr 0.3 Ca 0.7 MnO 3 (PCMO). With the same approach as of [1], we simulate a three-layer neural network with training accuracy > 90% on the MNIST dataset. The higher ON/OFF conductance ratio of improved Al/Mo/PCMO devices together with new programming strategies can lead to further accuracy improvement. Finally, we show that the bidirectional programming of Al/Mo/PCMO can be used to implement high-density neuromorphic systems with a single conductance per synapse, at only a slight degradation to accuracy.
We have developed a numerical simulation framework for HfO 2 based Ferroelectric Tunnel Junction (FTJ) memory using Non-Equilibrium Green Function (NEGF) and self-consistent potential method which is calibrated by our experimental FTJ results. Scalability and design guideline of Metal-Ferroelectric-Insulator-Semiconductor (MFIS) structure FTJ is investigated in this work. Due to the large asymmetry of dielectric screening length of MFIS structure FTJ electrodes, MFIS structure FTJ shows a higher tunneling electroresistance (TER) ratio than Metal-Ferroelectric-Insulator-Metal (MFIM) structure FTJ, while it has almost the same read current as MFIM structure FTJ. High read current and high TER ratio can be obtained by adjusting property of semiconductor bottom electrodes. A guideline of designing MFIS structure FTJ has been proposed for high read current and high TER ratio. MFIS type FTJ shows a potential for scaling down to sub-20 nm diameter.
