Molecular electronics is one of the revolutionary platforms to perform computation. In molecular quantum-dot cellular automata (mQCA), binary information can be encoded in candidate molecules by single charge localization, and logic operation is performed by using electrostatic interactions among neighboring cells. However, charge detection at the molecular level is extremely challenging. In this letter, we have fabricated two isolated sub-20-nm metal dots interconnected by a tunnel barrier that mimics an mQCA cell. Using a novel charge cancelation scheme, we observe robust detection of electron switching in the double-dot structure by a single-electron transistor at a temperature of 2.7 K. The experimentally observed period of single-electron charging in the double dots is in good correlation with COMSOL multiphysics’ simulations.

A radio frequency (RF) reflectometry technique is presented to measure device capacitances using a probe station. This technique is used to characterize micro-electromechanical system (MEMS) variable capacitor devices that can be connected to create pull-up and pull-down networks used in digital gates for reversible computing. Adiabatic reversible computing is a promising approach to energy-efficient computing that can dramatically reduce heat dissipation by switching circuits at speeds below their RC time constants, introducing a trade-off between energy and speed. The variable capacitors in this study will be measured using single port RF reflectometry achieved with a custom-made RF probe. The RF probe consists of a micromanipulator with an on-board matching network and is calibrated by measuring a capacitive bank that shows a clearly visible frequency shift with the increase in capacitance. The RF probe worked well when measuring static capacitors with no parasitic resistance; however, the frequency shift is masked when measuring the MEMS variable capacitors due to their high in-series parasitic resistance (around 80 kΩ). Therefore, RF reflectometry has the potential to measure MEMS variable capacitors in the range of 0-30 fF when not masked by a high in-series parasitic resistance, creating a fast and versatile method for characterizing variable capacitors that can be used in energy-efficient computing.

Abstract Sensitive dispersive readouts of single-electron devices (“gate reflectometry”) rely on one-port radio-frequency (RF) reflectometry to read out the state of the sensor. A standard practice in reflectometry measurements is to design an impedance transformer to match the impedance of the load to the characteristic impedance of the transmission line and thus obtain the best sensitivity and signal-to-noise ratio. This is particularly important for measuring large impedances, typical for dispersive readouts of single-electron devices because even a small mismatch will cause a strong signal degradation. When performing RF measurements, a calibration and error correction of the measurement apparatus must be performed in order to remove errors caused by unavoidable non-idealities of the measurement system. Lack of calibration makes optimizing a matching network difficult and ambiguous, and it also prevents a direct quantitative comparison between measurements taken of different devices or on different systems. We propose and demonstrate a simple straightforward method to design and optimize a pi matching network for readouts of devices with large impedance, $$Z \ge 1\hbox {M}\Omega$$ Z ≥ 1 M Ω . It is based on a single low temperature calibrated measurement of an unadjusted network composed of a single L-section followed by a simple calculation to determine a value of the “balancing” capacitor needed to achieve matching conditions for a pi network. We demonstrate that the proposed calibration/error correction technique can be directly applied at low temperature using inexpensive calibration standards. Using proper modeling of the matching networks adjusted for low temperature operation the measurement system can be easily optimized to achieve the best conditions for energy transfer and targeted bandwidth, and can be used for quantitative measurements of the device impedance. In this work we use gate reflectometry to readout the signal generated by arrays of parallel-connected Al-AlOx single-electron boxes. Such arrays can be used as a fast nanoscale voltage sensor for scanning probe applications. We perform measurements of sensitivity and bandwidth for various settings of the matching network connected to arrays and obtain strong agreement with the simulations.

The proposal of fault-tolerant quantum computations, which promise to dramatically improve the operation of quantum computers and to accelerate the development of the compact hardware for them, is based on topological quantum field theories, which rely on the existence in Nature of physical systems described by a Lagrangian containing a non-Abelian (NA) topological term. These are solid-state systems having two-dimensional electrons, which are coupled to magnetic-flux-quanta vortexes, forming complex particles, known as anyons. Topological quantum computing (TQC) operations thus represent a physical realization of the mathematical operations involving NA representations of a braid group B n , generated by a set of n localized anyons, which can be braided and fused using a “tweezer” and controlled by a detector. For most of the potential TQC material systems known so far, which are 2D-electron–gas semiconductor structure at high magnetic field and a variety of hybrid superconductor/topological-material heterostructures, the realization of anyon localization versus tweezing and detecting meets serious obstacles, chief among which are the necessity of using current control, i.e., mobile particles, of the TQC operations and high density electron puddles (containing thousands of electrons) to generate a single vortex. Here we demonstrate a novel system, in which these obstacles can be overcome, and in which vortexes are generated by a single electron. This is a ~ 150 nm size many electron InP/GaInP 2 self-organized quantum dot, in which molecules, consisting of a few localized anyons, are naturally formed and exist at zero external magnetic field. We used high-spatial-resolution scanning magneto-photoluminescence spectroscopy measurements of a set of the dots having five and six electrons, together with many-body quantum mechanical calculations to demonstrate spontaneous formation of the anyon magneto-electron particles ( e ν ) having fractional charge ν = n / k, where n = 1–4 and k = 3–15 are the number of electrons and vortexes, respectively, arranged in molecular structures having a built-in (internal) magnetic field of 6–12 T. Using direct imaging of the molecular configurations we observed fusion and braiding of e ν - anyons under photo-excitation and revealed the possibility of using charge sensing for their control. Our investigations show that InP/GaInP 2 anyon-molecule QDs, which have intrinsic transformations of localized e ν - anyons compatible with TQC operations and capable of being probed by charge sensing, are very promising for the realization of TQC.

Quantum dot Cellular Automata (QCA) is one of the developing patterns in the field of nanotechnology, which is supposed to overcome the constraints of CMOS innovation while integrated to nano-level. QCA can be utilized to structure memory circuits. Static Random Access Memory (SRAM) is one of the appealing utilization of QCA Innovation. The proposed plan and simulation of memory cell dependent on QCA with minimum area and complexity. This paper presents the design and simulation of multiport SRAM in QCA with least number of majority gates and it will be simulated using QCA Designer. SRAM based on QCA has been contrasted with CMOS innovation utilizing Xilinx. The comparison results show that the QCA memory circuit provides high efficiency in terms of area, complexity and power consumption. QCA can be used to design memory circuits. Static Random Access Memory (SRAM) is one of the attractive application with QCA Technology. The proposed design and simulation of memory cell based on QCA with minimum area and complexity. This paper presents the design and simulation of multiport SRAM in QCA with minimum number of majority gates. SRAM based

Reversible computing is a promising approach to energy efficient computing that reduces heat generation by introducing a trade-off between energy and speed. The most developed approach to reversible computing is adiabatic CMOS, but its lowest energy dissipation is still limited by passive power, the energy wasted due to leakage current caused simply by applying a voltage to the circuit. A new approach, Adiabatic Capacitive Logic (ACL), implements reversible computing by using variable capacitors as pull-up and pull-down networks. ACL eliminates leakage current and therefore is not limited by passive power. We present the design and proposed nanofabrication of gap-closing voltage-controlled variable capacitors to implement ACL as a future computing approach.

Single-electron tunneling transistors (SETs) and boxes (SEBs) exploit the phenomenon of Coulomb blockade to achieve unprecedented charge sensitivities. Single-electron boxes, however, despite their simplicity compared to SETs, have rarely been used for practical applications. The main reason for that is that unlike a SET where the gate voltage controls conductance between the source and the drain, an SEB is a two terminal device that requires either an integrated SET amplifier or high-frequency probing of its complex admittance by means of radio frequency reflectometry (RFR). The signal to noise ratio (SNR) for a SEB is small, due to its much lower admittance compared to a SET and thus matching networks are required for efficient coupling ofSEBs to an RFR setup. To boost the signal strength by a factor of N (due to a random offset charge) SEBs can be connected in parallel to form arrays sharing common gates and sources. The smaller the size of the SEB, the larger the charging energy of a SEB enabling higher operation temperature, and using devices with a small footprint (<0.01 µm2), a large number of devices (>1000) can be assembled into an array occupying just a few square microns. We show that it is possible to design SEB arrays that may compete with an SET in terms of sensitivity. In this, we tested SETs using RF reflectometry in a configuration with no DC through path (“DC-decoupled SET” or DCD SET) along with SEBs connected to the same matching network. The experiment shows that the lack of a path for a DC current makes SEBs and DCD SETs highly electrostatic discharge (ESD) tolerant, a very desirable feature for applications. We perform a detailed analysis of experimental data on SEB arrays of various sizes and compare it with simulations to devise several ways for practical applications of SEB arrays and DCD SETs.

Single-electron tunneling transistors (SETs) and boxes (SEBs) belong to the family of charge-sensitive electronic devices based on the phenomenon of Coulomb blockade. An SEB is a two-terminal device composed of “leaky,” Cj, and “non-leaky,” Cg, nanoscaled capacitors in series. At low temperatures, the charge at the common node is quantized and can only be changed near energy-population degeneracy points, resulting in periodic oscillations of the SEB admittance as a function of voltage applied to Cg. In comparison to the SETs, SEBs have higher operating temperature, are electrostatic discharge tolerant, and have a much smaller footprint. To monitor the SEB admittance, Radio Frequency reflectometry can be used. To improve the signal-to-noise ratio, limited by the small change in admittance in an SEB, multiple devices sharing the same source and gate electrodes are connected in parallel to form arrays of SEBs. Due to unavoidable random offset charges, the signal boost for an array of N SEBs is expected to be ∼N. We experimentally demonstrate that by carefully choosing the operating point, the response to the voltage on the sensing gate can be enhanced, for small arrays scales, by a factor approaching N and, thus, provides a method by which these devices can be used in practical sensing applications, such as a scanning probe.

Random numbers are a valuable commodity in gaming and gambling, simulation, conventional and quantum cryptography, and in non-conventional computing schemes such as stochastic computing. We propose to generate a random bit using a position measurement of a single mobile charge on a coupled pair of quantum dots. True randomness of the measurement outcome is provided by quantum mechanics via Born's rule. A random bit string may be generated using a sequence of repeated measurements on the same double quantum dot (DQD) system. Any bias toward a "0" measurement or a "1" measurement may be removed or tuned as desired simply by adjusting the detuning between localized states. Device tunability provides versatility, enabling this quantum random number generator (QRNG) to support applications in which no bias is desired, or where a tunable bias is desired. We discuss a metal-dot implementation as well as a molecular implementation of this QRNG. Basic quantum mechanical principles are used to study power dissipation and timing considerations for the generation of random bit strings. The DQD offers a small form factor and, in a metallic implementation, is usable in the case where cryogenic operations are desirable (as in the case of quantum computing). For room-temperature applications, a molecular DQD may be used.

Heat production is one of the main limiting factors in modern computing. In this paper, we explore adiabatic reversible logic which can dramatically reduce energy dissipation and is a viable implementation of future energy-efficient computing. We present a 16-bit adiabatic microprocessor with a multicycle MIPS architecture designed in 90nm technology. The adiabatic circuits are implemented using split-rail charge recovery logic, which allows the same circuit to be operated both in adiabatic mode and in standard CMOS mode. Simulations of a shift register show that energy dissipation can be much lower when operating in adiabatic mode compared to its CMOS counterpart. We present a standard cell library with all the necessary components to build adiabatic circuits and implement the subsystems of the microprocessor. The microprocessor has a proposed operating frequency of 0.5 GHz representing a useful implementation of adiabatic reversible computing.

In this paper, we present results demonstrating the effect of temperature on singularity matching (SM) tunneling down to 300 mK in superconducting single-electron transistors (SSETs). The studied SSETs have charging energies significantly larger than the Josephson energy, which makes it possible to study the SM condition without other sub-superconducting gap conduction mechanisms obscuring the SM signatures at low biases. The presence of parity in one such device has also allowed us to explore the effect of temperature on the effect of parity on SM features.

Over the past five years, fabrication of metal-insulator-metal (MIM) single electron transistors (SET) featuring atomic layer deposition (ALD) of ultrathin tunnel barrier dielectrics (SiO2, Al2O3) has been reported. However, the performance of fabricated devices was significantly compromised by the presence of native metal oxide and problems associated with the nucleation of ALD dielectrics on metal substrates. To overcome the difficulty of dielectric ALD nucleation on metal substrates, we recently developed a fabrication technique in which the native metal oxide naturally forming in the presence of the ALD oxidant precursor is first used to promote the nucleation of ALD dielectrics, and then is chemically reduced by forming gas anneal (FGA) at temperatures near 400 °C. However, despite the elimination of native oxide, low temperature characterization of the devices fabricated using FGA reveals excess 'switching' noise of a very large magnitude resulting from charged defects within the junctions. It has been previously reported that remote hydrogen plasma (RHP) treatment of SiO2 thin films effectively eradicates fabrication defects. This work reports a comparative study of Ni-based MIM SET treated with FGA and/or RHP. We show that, using a combination of FGA and RHP treatments, it is possible to obtain MIM junctions free of switching noise and without a detectable contribution of native oxide.

We report, for the first time, a gate last process, used to fabricate Negative Capacitance field effect transistors (NCFETs) with Hf 0.5 Zr 0.5 O 2 (HZO) as ferroelectric (FE) dielectric in a metal/ferroelectric/insulator/semiconductor (MFIS) configuration. Long channel NCFET's with HZO thickness down to 5 nm exhibit consistent switching behavior with switching slope (SS rev ) below kT/q over four decades of drain current. Temperature dependent transport study shows that, the effective mobility of HZO NCFETs is 15 % higher than that of HfO 2 based control MOSFETs due to suppression of Hf diffusion into the interfacial SiO 2 layer (IL). Using the Preisach hysteresis model, which models dynamics of FE switching through a cluster of independent switching dipoles at arbitrary electric field, we (a) explain the asymmetric SS behavior of NCFETs in MFIS configuration, and (b) establish design guidelines for achieving sub-kT/q SS in both forward and reverse sweep direction.

This paper examines adiabatic logic for computation, and presents a design for a MIPS processor implemented in CMOS. Adiabatic reversible logic was examined in the 1980s and 1990s but in that era power dissipation was a secondary concern, and the trade-off of reduced computational speed for reduced power was deemed unacceptable. Now, power dissipation and the associated heat are the major obstacles limiting progress in integrated circuits, particularly processors. In modern processors trading performance for reduced power dissipation is already done using techniques such as multi-core and dark silicon, so adiabatic logic may now be an attractive approach. To evaluate the adiabatic approach, this paper uses the figure of merit of the product of switching energy, delay time, and area (EDA). Using this figure of merit, adiabatic logic is shown to be advantageous when additional constraints are considered, such as maximum allowed power density. As a proof of concept circuit, a simplified MIPS microprocessor was designed using adiabatic logic based on split-rail charge recovery logic and Bennett clocking. New design and verification tools were developed using structural Verilog and extensions of ModelSim to provide needed capabilities are not available in commercial packages. The design is implemented using a standard cell design.

This work describes the fabrication of single electron transistors using electron beam lithography and atomic layer deposition to form nanoscale tunnel transparent junctions of alumina (Al2O3) on platinum nanowires using either water or ozone as the oxygen precursor and trimethylaluminum as the aluminum precursor. Using room temperature, low frequency conductance measurements between the source and drain, it was found that devices fabricated using water had higher conductance than devices fabricated with ozone. Subsequent annealing caused both water- and ozone-based devices to increase in conductance by more than 2 orders of magnitude. Furthermore, comparison of devices at low temperatures (∼4 K) showed that annealed devices displayed much closer to the ideal behavior (i.e., constant differential conductance) outside of the Coulomb blockade region and that untreated devices showed nonlinear behavior outside of the Coulomb blockade region (i.e., an increase in differential conductance with source-drain voltage bias). Transmission electron microscopy cross-sectional images showed that annealing did not significantly change device geometry, but energy dispersive x-ray spectroscopy showed an unusually large amount of oxygen in the bottom platinum layer. This suggests that the atomic layer deposition process results in the formation of a thin platinum surface oxide, which either decomposes or is reduced during the anneal step, resulting in a tunnel barrier without the in-series native oxide contribution. Furthermore, the difference between ozone- and water-based devices suggests that ozone promotes atomic layer deposition nucleation by oxidizing the surface but that water relies on physisorption of the precursors. To test this theory, devices were exposed to forming gas at room temperature, which also reduces platinum oxide, and a decrease in resistance was observed, as expected.

Single electron transistors (SET) featuring metal (Ni) electrodes and silicon nitride dielectric barriers prepared by atomic layer deposition are fabricated and tested. Electrical characterization of the devices reveals electrostatic energy parameters consistent with the parameters of the designed tunnel junctions. In addition, an analysis of temperature dependence of conductance confirms the formation of metal-insulator-metal (MIM) junctions with negligible in-series contribution of any surface native metal oxide. However, the fabricated devices exhibit a very high level of electrical noise, far exceeding the commonly observed shot noise. Experimental investigation reveals the random telegraph signal (RTS) nature of the observed excess noise. The RTS noise in electronic devices is commonly associated with charging of external traps that are electrostatically coupled to the SET island. In the devices under study, however, the defects that result in the observed RTS noise are demonstrated to reside within the tunnel junctions. Our results also indicate the critical importance of interface states and surface preparation for achieving good performance of the SETs fabricated using ALD to form the tunnel barrier.

Recently developed dual port reflectometric spectroscopy (DPRS) not only enables detection of single electron charging events in nanoscaled MOS single-electron transistors (SETs) that are not detectable using conventional transport spectroscopy, but DPRS also provides the ability to spatially localize charging events and discriminate between charging events involving defects and those associated with the SET island. Here we present an experimental study of charging processes in Si single-hole transistors (SHTs) from deep depletion (prior to electrostatic formation of the island) through the initial stages of SHT island formation and population with the first few holes.

We report the use of plasma-enhanced atomic layer deposition (PEALD) to fabricate single-electron transistors (SETs) featuring ultra-thin (~1 nm) tunnel-transparent SiO2 in Ni-SiO2-Ni tunnel junctions. We show that as a result of the O2 plasma steps in PEALD of SiO2, the top surface of the underlying Ni electrode is oxidized. Additionally, the bottom surface of the upper Ni layer is also oxidized where it is in contact with the deposited SiO2, most likely as a result of oxygen-containing species on the surface of the SiO2. Due to the presence of these surface parasitic layers of NiO, which exhibit features typical of thermally activated transport, the resistance of Ni-SiO2-Ni tunnel junctions is drastically increased. Moreover, the transport mechanism is changed from quantum tunneling through the dielectric barrier to one consistent with thermally activated resistors in series with tunnel junctions. The reduction of NiO to Ni is therefore required to restore the metal-insulator-metal (MIM) structure of the junctions. Rapid thermal annealing in a forming gas ambient at elevated temperatures is presented as a technique to reduce both parasitic oxide layers. This method is of great interest for devices that rely on MIM tunnel junctions with ultra-thin barriers. Using this technique, we successfully fabricated MIM SETs with minimal trace of parasitic NiO component. We demonstrate that the properties of the tunnel barrier in nanoscale tunnel junctions can be evaluated by electrical characterization of SETs.

Gate-coupled reflectometric spectrometry has recently emerged as a tool for studies of transport in nanostructures. Here we report reflectometric spectroscopy of a double-gate single electron device in which two coupled quantum dots are formed under the gates. The spectroscopy is performed by detection of charging processes in the system using a dual port reflectometer. The potential application of this scheme for detection of qubits is also discussed.

A1. (Invited) Deep UV LEDs with GaN/AlN quantum structures using polarization-induced doping SM Islam, Vladimir Protasenko, Sergei Rouvimov, Samira Chandra, Jai Verma, Huili (Grace) Xing, and Debdeep Jena The 230-270 nm emission is very attractive for water purification, sterilization application, diagnostics and hazardous chemicals detection. Unfortunately, LED devices emitting at short wavelengths and utilizing AlGaN for active area suffer significant energy losses due to non-radiative recombination near structural defects. Replacing AlGaN with ultra-thin GaN quantum wells (QWs) and quantum dots (QDs) and AlN for barriers can solve this problem due to better carrier localization in quantum dots, absence of compositional variation in GaN/AlN structure, and better light extraction with TE polarized emission. Also traditional impurity doping schemes are difficult for such high Al content AlGaN alloys due to the large activation energies of dopants. In order to solve the issue of doping, polarization-induced (or Pi-) doping scheme is used in the devices. In this work, we experimentally demonstrate electrically injected tunable deep UV emission from GaN/AlN quantum structures. The emission wavelength is tuned over 231 nm→270 nm range by changing thickness of GaN layer placed between similar thicknesses of AlN barrier. We grew the LED structures on commercially available AlN templates on Sapphire with a threading dislocation density of ~1e10 cm-2 using plasma assisted molecular beam epitaxy (PAMBE). Polarization doping (Pidoping) is established by changing the chemical composition linearly for both p and n doped regions of the LED structures. The Pi-doping ensures flat bands for both electrons and holes in the n and p doped regions respectively which facilitates smooth injection of carriers into the active region that emits the light. Thin AlN barriers in the active region enables tunneling of carriers which further enhances carrier injection. We grew 1-4 monolayers (MLs) thick GaN QDs by Stranski-Krastanov mode between 2 nm thick AlN barriers. By varying the GaN thickness, the emission wavelength can be tuned over 231-270 nm range. A2. Surface Plasmon Propagation in Cut Waveguides Paul Johns and Gregory Hartland Nanoscale optical waveguides can be used to create nano-circuits, perform logic functions, split signals, or aid in the development of plasmonic lasers. In these applications, long propagation lengths and control of the modes is desireable. Developing plasmonic devices requires an under-standing of how defects in the waveguides affect propagation, and how plasmons couple between devices. An example of a plasmonic waveguide is a gold nanobar (a nanowire with a rectangular cross-section), which supports bound and leaky propagating surface plasmon polaritons. Defects were introduced into single-crystalline gold nanobars by cutting them in several places using FIB milling. Plasmons were launched using end-fire coupling, and a pump-probe spectroscopy technique was used to directly image the plasmon propagation in the nanobars. The intensity of the plasmon mode was shown to decrease at the cuts. Finite element method calculations as implemented by COMSOL Multiphysics were used to study how the mode shapes were changed by the discontinuities and to study damping of the modes during propagation. The results of the calculations are in good agreement with the experiments, and show that a resonance effect occurs at gap sizes of ~30 nm. It was determined that of the two primary modes that propagate through the structures, the leaky mode (which occurs at the interface of air and gold) is heavily damped by the cut while the bound mode (which occurs at the interface of glass and gold) is not as severely affected. A3. Engineering the Reststrahlen Band with Hybrid Plasmonic/Phononic Modes W. Streyer, K. Feng, Y. Zhong, A.J. Hoffman, and D. Wasserman The so called phononic materials has drawn more and more interest because of their superiorities over the traditional plasmonic materials in the mid-infrared (mid-IR) spectral range. Comparing to the surface plasmon polaritons (SPP), the surface phonon polaritons (SPhP) supported by phononic materials suffer from much smaller material loss, which can result in longer propagation length and higher Q factors in propagation and localized modes, respectively. However, the SPhP modes are confined within the spectral range between a material’s transvers and longitudinal phonon frequencies, also known as the Reststrahlen band. In order to break the limitation of the fixed spectral range for SPhP modes, here we demonstrate that for materials with appropriate free carrier concentration, the hybrid surface plasmon/phonon polariton (SPPhP) modes can be supported across a range of frequencies including those generally forbidden by purely phononic materials. In this work, we first characterize the intrinsic and doped GaAs samples by measuring their reflection spectra around the Reststrahlen band of GaAs. The samples are then patterned with gratings so that the incident light can couple to the surface of the samples as SPhP or SPPhP modes. The reflection spectra of TE polarized light with different azimuth angels are obtained from both RCWA simulation and measurements. Dispersion curves of the hybrid modes are calculated and mapped out based on the RCWA simulations. The TM reflection spectra are also acquired in the same way. It is observed that localized resonance modes have been excited around the LO phonon frequency of GaAs, which can be the potential bridge between LO phonons and free space photons at the same energy. A4. Application of critical dimension metrology techniques for the fabrication of low loss optical waveguides Yuan Tian and Douglas C. Hall For Silicon photonics applications aimed towards integrating light-emitting compound semiconductors with Si electronics integrated circuits, wafer bonding is often preferred to III-V heteroepitaxial growth on Si for its smaller resulting density of interface misfit dislocations and other advantages. Oxide to oxide wafer bonding, where strong bonding can be formed at annealing temperatures <350°C, is essential when bonding GaAs or InP wafers to Si in order to avoid thermal dissociation of the compound semiconductor and issues related to mismatched coefficients of thermal expansion. We propose and demonstrate that optimized III-V compound semiconductor wet thermal native oxides with low surface roughness, typically < 1 nm, offer additional flexibility for photonic/silicon wafer bonding, as the surface roughness can readily meet the sub-nm requirement even for thick oxide layers. The method can be applied through oxidation of a variety of III-V compound semiconductor alloys used in both GaAs and InP systems. Compared to other complicated pre-bonding treatment processes including fabrication of outgassing channels and plasma activation, our wet thermal native oxide mediated bonding technique may enable a more reliable, lower cost process readily applicable to large scale wafer bonding. Possible applications include the development of broadband, low-cost on-chip Erbium-doped waveguide amplifiers employing InAlP thermal native oxides (a promising rare earth host), and the improved fabrication of silicon hybrid lasers to combine the communication advantages of photonic devices with well-established Si CMOS fabrication techniques. Preliminary calculations suggest that both oxidation and annealing steps can be achieved under 350°C to avoid known thermal degradation mechanisms in InP-based quantum well laser heterostructures. Experiments demonstrating successful low temperature wafer bonding of compound semiconductors with thin wet thermal native surface oxides to oxidized Si wafers will be discussed. A5. Application of critical dimension metrology techniques for the fabrication of low loss optical waveguides Zachary C. Santonil and Douglas C. Hall This talk presents the use of critical dimension (CD) metrology as a means to optimize the fabrication of low-loss deepetched high-index contrast (HIC) III-V compound semiconductor waveguide structures. HIC waveguides have been a topic of interest in the area of photonic integration in that they can be used to attain micrometer bend radii as opposed to the millimeter band radii exhibited by conventional waveguide structures. However, as the lateral refractive index contrast increases, these structures are much more susceptible to scattering loss due to sidewall roughness. Previous work conducted by our research group has focused on improving sidewall roughness through an isotropic oxidation smoothing process. In order to realize the lowest possible loss HIC waveguides, it is essential to further optimize each fabrication stage in order to fully minimize the final sidewall roughness accumulated after several processing steps. Thus, CD metrology was recently implemented with the intention of extracting quantifiable and relative metrics to observe the various contributions to sidewall roughness introduced throughout the fabrication of the waveguide structure. Using modern line digitization techniques with the SuMMIT CD Suite on images obtained through scanning electron microscopy, fabrication steps can be analyzed and optimized by comparing various CD metrics – in particular – line edge roughness (LER) and correlation length (Lc). For waveguide optimization, reduced LER is always desirable, whereas the more complex relationship between waveguide loss and correlation length is nonmonotonic and depends on the waveguide geometry. This talk will discuss the implementation of line digitization techniques to obtain the LER and Lc of waveguide processing steps such as lithography, pattern transfer to a hard silicon nitride etch mask, and inductively coupled plasma reactive ion etching of the waveguide ridge structure. Various other process improvements useful for achieving reduced sidewall roughness for low HI