Silicon photonics is of great interest as it opens the way to large bandwidth and high data rates. A pioneer Silicon photonics scheme consists in integrating III-V lasers on the SOI substrates containing the passive components. However, key developments are necessary to co-integrate III-V devices with CMOS very large scale integration (VLSI). In this paper we propose a CMOS-compatible integration scheme of contacts (i.e. semiconductor metallization and plug) on III-V surfaces taking into account the limitations fixed by the operating laser device. Based on metallurgical, morphological, optical and electrical studies, processes are submitted and reviewed for the purpose of forming stable and reproducible contacts with low resistivity in a 200 millimeters fab line.

Here, we demonstrate a new process to fabricate tensily strained Si On Insulator substrates (sSOI). The process is based on the epitaxial growth of Si1-xGex on SOI substrate, the partial amorphization and crystallization of the Si/Si1-xGex bilayers and the selective removal of the top Si1-xGex film. Si tensile stress higher than 1.4 GPa is obtained. Complementary Metal Oxide Semiconductor Fully Depleted-SOI (CMOS FD-SOI) devices, with gate length lower than 15 nm, were fabricated on top of such substrate. For nFET devices, improvement in mobility is demonstrated with respect to devices built on standard SOI substrates. (C) The Author(s) 2015. Published by ECS. All rights reserved.

We demonstrate the fabrication of strained Si-On-Insulator (sSOI) using a relaxation process of a compressive SiGe layer on SOI, and the transfer of lattice parameter from the relaxed SiGe to the Si layer. This process is based on a partial amorphization and recrystallization of the SiGe/Si stack. We used HRXRD (High Resolution X-Ray Diffraction) and TEM (Transmission Electron Microscopy) to characterize the microstructure of the layers. Strain and Stress evolutions throughout the process were determined using Raman spectroscopy and wafer bow measurements. Using a stack of 40 nm Si0.7Ge0.3 on 9 nm Si, we obtained tensile Si layer having a stress of + 1.6 GPa which corresponds to a 80% lattice parameter transfer from SiGe to Si.

The disilane (Si2H6)+germane (GeH4) chemistry has been evaluated for the reduced pressure (2660Pa, i.e. 20Torr), low temperature growth of intrinsic and heavily boron-doped SiGe. A SiGe growth rate “plateau” has been evidenced between 650°C and 750°C. Meanwhile, the Ge concentration x was rather steady in the 500°C–700°C range. A linear increase of the SiGe growth rate with the GeH4 flow occurred at 500°C, 550°C and 675°C. The increase of x with the GeH4 mass-flow otherwise changed from linear to sub-linear as the growth temperature was reduced from 675°C down to 500°C–550°C. Be it with Si2H6 or SiH4, the SiGe growth rate fell by a factor of ~7–8 when switching from 550°C to 500°C. For the same x, growth rate was nevertheless 3–9 times higher with Si2H6 than with SiH4. We have also studied the impact of B2H6 on the 500°C growth kinetics of SiGe with Si2H6. Large substitutional boron concentrations were obtained in single-crystalline SiGe:B layers: [B]subst.~3.7×1020 cm−3. Surface B atoms otherwise catalysed H desorption, resulting in growth rates ~5 times higher for SiGe:B than for intrinsic SiGe. Finally, a monotonic decrease of the SiGe(:B) growth rate together with a significant increase of the Ge concentration were evidenced at 500°C and 675°C when adding HCl to the gaseous mixture. At 500°C, SiGe:B growth rates still stayed 3 times higher than the intrinsic SiGe ones. Adding HCl had otherwise no clear impact on [B]subst.

Metallization method of a porous material comprising depositing metallic material in the liquid phase with a solution comprising metal ions, deposition temperature, pH of the solution, and metal ion concentration of the solution being chosen so as to allow less than or equal deposition rate 0.1 nm / min.

Porous silicon (PSi) layers are used as templates to grow epitaxial planar and fully relaxed Ge pseudo-substrates. An annealing at 600 °C, dramatically changes the PSi morphology and produces compliant template layers which serve in a second step, as substrate for the epitaxy of fully relaxed SiGe layers with a Ge content between 50% and 94%. The SiGe pseudo-substrates produced by such process exhibit a remarkable planar surface resulting from the penetration of Ge inside the pores. They could be integrated into conventional microelectronic technology for the subsequent deposition of active layers such as tensily strained Si or relaxed Ge.

We have studied the porous silicon (PS) formation dependence on the substrate doping concentration as a selective tool to form locally oxidized regions in silicon wafers. This approach could be used for electrical isolation in CMOS circuits as a promising alternative to the shallow trench isolation STI process which begins to show some limitations (voiding and dishing) for the most advanced technologies.

In this study we investigate the mechanisms of growth and boron (B) incorporation into crystalline silicon (c-Si) during crystallization of amorphous doped silicon (a-Si:B) films. The process developed consists of two steps, first the chemical vapor codeposition at low temperature of Si and B atoms to form a-Si:B layer and second the crystallization of amorphous phase during in situ annealing to incorporate boron atoms on the substitutional sites of c-Si. We find that the crystallization rate linearly increases with the nominal boron concentration (CB) up to a critical CB∗ which corresponds to the maximum concentration of electrically active boron atoms in the crystalline phase. In these conditions, an increase in the crystallization rate by a factor 22 as compared to the intrinsic crystallization rate is obtained. We suggest that this remarkable behavior is attributed to D+ charged defects associated to the activated doping atoms in agreement with the generalized Fermi level shifting model. For larger CB, further boron atoms are incorporated in the amorphous phase in the form of ultrasmall clusters that do not contribute to shift the Fermi level of a-Si. As a consequence, for CB>CB∗ the crystallization rate does not increase any more. We also show that crystallization provides a more complete incorporation of boron atoms already present in a-Si than the codeposition of Si and B atoms in the same experimental conditions (same growth rate and temperature). This result is attributed to the lower kinetic segregation at the amorphous-crystalline (a/c) interface than at the vacuum-crystalline interface. The lower kinetic segregation results from both a higher diffusion barrier of boron atoms at the a/c interface and a lower segregation energy (due to a low a/c interface energy).

We show that chemical vapor deposition using trisilane decomposition opens capabilities for the deposition of amorphous silicon on Si substrate at low temperature. Based on this behavior we developed a process including amorphous silicon deposition and crystallization. Transmission electron microscopy observations prove that solid phase epitaxy (SPE) occurs and produces monocrystalline layers, free of extended defects and compatible with complementary metal-oxide-semiconductor technology. We also show that during SPE films remain amorphous on oxidized areas while they transform into single crystal on Si. This process opens promising perspectives for the fabrication of advanced MOS structures.

J.-L. Huguenin1,2, S. Monfray1, G. Bidal1, S. Denorme1, P. Perreau3,1, N. Loubet1, Y. Campidelli1, M.-P. Samson1,3, C. Arvet1,3, K. Benotmane3, F. Leverd1, P. Gouraud1, B. Le-Gratiet1, C. De-Butet3,1, L. Pinzelli1, R. Beneyton1, S. Barnola3, T. Morel1, A. Halimaoui1,3, F. Boeuf1, G. Ghibaudo2, T. Skotnicki1. 1 ST Microelectronics, 860 rue Jean Monnet, 38926 Crolles, France ; 2IMEP-LAHC, 3 parvis Louis Néel, BP 257, 38016 Grenoble Cedex 1, France ; 3 CEA-LETI 17 rue des Martyrs, 38054 Grenoble, France

Ytterbium silicide provides a low Schottky barrier height to electron on n-type silicon. This property makes this material very attractive for the realization of Source/Drain contacts for n-type MOSFETs. In this communication, the study of structural and electrical properties of YbSi2-x fabricated at different temperature in Ultra-High Vacuum condition without any protective layers is presented. N-type SB-MOSFETs with ytterbium silicide based S/D contacts were fabricated at optimal silicidation temperatures on SOI substrate with an ultra thin body.

Advanced structures with poly-Si gates, Si3N4 spacers, and shallow trench isolation (STI) areas were used for elaborating the selective growth of Si1-yCy films into recessed source and drain (S/D).Selective Si1-yCy films were grown by repeated cycles consisting of two distinct steps: a non-selective CVD growth of Si1-yCy layers, and a chemical vapor etching with hydrochloric gas. This cyclic deposition/etching process has been experimented at 600 degrees C with a methylsilane/(methylsilane+trisilane+hydrogen) mass flow ratio (SiCH6 MFR) equal to 2.8 x 10(-4) used for Si0.99C0.01 film deposition. Regarding etching step, a pure HCl gas/(hydrogen) mass flow ratio (HCl MFR) was about 4.3 x 10(-1). We should note that the poly-crystalline Si1-yCy layers are etched more rapidly than the monocrystalline layers. The etching rate ratio between poly and mono areas induces the capability, by cyclic process, to remove the deposited poly-crystalline Si1-yCy layers on the dielectric areas (STI spacers) selectively versus the recessed mono-crystalline Si1-yCy layers. A global time process, of about 3 h, resulted in 50 nm thick Si0.99C0.01 films selectively grown into recessed S/D.The new TEM technique of dark-field holography was used to determine a mapping of the strain at transistor level (within Si channel among S/D);The tensile stress of about 0.2 GPa has been measured within Si channel (300 nm length) among recessed Si0.985C0.015 films. (C) 2009 Elsevier Ltd. All rights reserved.

Si homo-epitaxial growth by low-temperature reduced pressure chemical vapor deposition (RPCVD) using trisilane (Si3H8) has been investigated. The CVD growth of Si films from trisilane and silane on Si substrates are compared at temperatures between 500 and 950 °C. It is demonstrated that trisilane efficiency increases versus silane's one as the surface temperature decreases. Si epilayers from trisilane, with low surface roughness, are achieved at 600 and 550 °C with a growth rate equal to 12.4 and 4.3 nm min−1, respectively. It is also shown that Si1−xGex layers can be deposited using trisilane chemistry. The epitaxy of Si1−yCy films as stressors source and drain is a promising way to improve the performances of n-type MOS devices. To take advantage of the tensile-strained Si1−yCy films, the level of carbon into substitutional sites must be significant (⩾1%). Such levels of substitution require low growth temperatures (<650 °C) and high growth rates. Using trisilane and methylsilane gases, the highest substitutional carbon concentrations incorporated are 1.9% at 600 °C and 2.3% at 550 °C with growth rates equal to 20 and 7 nm min−1, respectively. Stress values of about few gigapascals have been measured on blanket Si1−yCy films.

Based on the recently developed MCs2+ secondary ion mass spectrometry methodology, the Ge–Si interdiffusion has been investigated, using Ge(:B) solid sources, for Ge concentrations between 0 and 100 at. %. A strong dependence of the interdiffusion with the Ge content of SiGe alloys, formed during annealing, has been shown. The Boltzmann–Matano method was used to extract the interdiffusivity values for all the temperatures studied (750, 800, 850, and 900 °C) in the full range of SiGe compositions. Two regimes of interdiffusion have been identified, both exhibiting an exponential increase in the interdiffusion coefficient as a function of the Ge concentration. The high Ge content regime (>65 at. %) is in good agreement with the values known in the “extreme” cases of Ge diffusion in Si (0 at. %), Ge self-diffusion, and Si diffusion in Ge (100 at. %), while in the low Ge content regime (<50 at. %), the presence and evolution of misfit dislocation can explain the important values of interdiffusivity found in t...

In this letter, an original selective etching method of Pt with respect to PtSi using a sacrificial low-temperature germanidation process is used for the integration of valence band edge contacts in p-type MOSFET devices. After silicidation annealing, the excess of Pt due to incomplete reaction with silicon or standing on insulating layers can be transformed into the PtGe2 phase. The solubility of this phase in a sulfuric peroxide mixture (SPM) without altering PtSi is demonstrated. The suitability and scalability of the proposed integration scheme is shown through the successful integration and characterization of PtSi source/drain contacts in p-type MOSFETs.

This paper reports on advances in metallic source/drain MOSFETs covering material engineering, integration issues such as metal/silicide selective etching and electrical performance in both DC and RF regimes. A soft and scalable etching procedure that selectively eliminates metallic platinum (Pt) without altering the platinum silicide phase (PtSi) is proposed. Strategies of Schottky barrier reduction based on low temperature dopant segregation are exemplified when PtSi is coupled to boron and arsenic. Finally, the integration of p-type boron-segregated contacts in thin-film SOI p-MOSFETs reveals state-of-the-art results both for DC and RF operation.

In this work we present results on sub-melt Excimer laser annealing in order to obtain difussionless activation of Boron for the creation of ultra shallow P-MOS devices. For the fulfillment of the strict requirements imposed by the ITRS roadmap for the 32nm node we have implemented two emerging techniques: non-melt laser annealing and BF3 Plasma Doping implantation (PLAD). By using PLAD, we were able to create ultra shallow and abrupt as implanted profiles. On the other hand, by performing laser annealing on the samples in the sub-melt regime, we can achieve high levels of electrical activation, while practically eliminating Boron diffusion, due to its capability to deliver low thermal budget in the sub-microsecond time scale. An Excimer KrF laser (λ=248nm and pulse duration 38ns) has been used. The post annealing characterization of the samples included SIMS and Van Der Pauw Sheet resistance measurements. SIMS data indicate almost difussionless dopant behavior with Rs values at 680Ω/sq. We have concluded our analysis with the examination of the morphological characteristics both of the surface of the sample using Atomic Force Microscopy (AFM) and the evolution of the recrystallization of the amorphized layers and the removal of the defects by means of cross-section Transmission Electron Microscopy.

A soft and scalable etching procedure that selectively eliminates Pt without altering PtSi is proposed. The selective etch is based on the low temperature transformation of the excess Pt into a more reactive PtxGey phase that is easily etched in a sulfuric peroxide mixture. The mechanism of PtxGey alloying is detailed based on x-ray diffraction analysis. The innocuousness of the germanidation-based selective etch on the integrity of the PtSi∕Si junction is consolidated by Schottky barrier measurements. This process is expected to facilitate the integration and the scalability of PtSi on ultrathin silicon layers.

We have studied the matrix effects in Si1−xGex structures under O2+ and Cs+ bombardments. Matrix effects are practically suppressed with Cs2Ge+ secondary ions, for Ge concentrations between 0 and 100at.%. A procedure for the accurate quantification of the Ge concentration in Si1−xGex alloys using Cs2Ge+ and CsGe+ clusters has been proposed. For structures in which the Ge content is constant over several hundreds of nanometers, both methods provide very similar results, with an excellent agreement between the Ge concentrations measured by secondary ions mass spectrometry and x-ray diffraction. However, for continuously varying Ge concentration profiles, the nonlinear response of the CsGe+ normalized intensity and the persistence of strong matrix effects for CsSi+ ions lead to differences between the Ge concentration profiles measured with the CsGe+ method compared to the Cs2Ge+ one. The latter is therefore the only reliable method for the study of Ge indiffusion into Si from a pure Ge layer grown by chemic...