This review paper covers a topic of significant importance in micro- and nano-systems development and manufacturing, specifically the residual stresses in deposited thin-film material layers and methods to control or mitigate their impact on device behavior. A residual stress is defined as the presence of a state of stress in a thin-film material layer without any externally applied forces wherein the residual stress can be compressive or tensile. While many material properties of deposited thin-film layers are dependent on the specific processing conditions, the residual stress often exhibits the most variability. It is not uncommon for residual stresses in deposited thin-film layers to vary over extremely large ranges of values (100% percent or more) and even exhibit changes in the sign of the stress state. Residual stresses in deposited layers are known to be highly dependent on a number of factors including: processing conditions used during the deposition; type of material system (thin-films and substrate materials); and other processing steps performed after the thin-film layer has been deposited, particularly those involving exposure to elevated temperatures. The origins of residual stress can involve a number of complex and interrelated factors. As a consequence, there is still no generally applicable theory to predict residual stresses in thin-films. Hence, device designers usually do not have sufficient information about the residual stresses values when they perform the device design. Obviously, this is a far less than ideal situation. The impact of this is micro- and nano-systems device development takes longer, is considerably more expensive, and presents higher risk levels. The outline of this paper is as follows: a discussion of the origins of residual stresses in deposited thin-film layers is given, followed by an example demonstrating the impact on device behavior. This is followed by a review of thin-film deposition methods outlining the process parameters known to affect the resultant residual stress in the deposited layers. Then, a review of the reported methods used to measure residual stresses in thin-films are described. A review of some of the literature to illustrate the level of variations in residual stresses depending on processing conditions is then provided. Methods which can be used to control the stresses and mitigate the impact of residual stresses in micro- and nano-systems device design and fabrication are then covered, followed by some recent development of interest.

This paper reviews the topic of the device parameter variations using semiconductor-based manufacturing of micro- and nano-devices. There is considerable misunderstanding about the precision of these types of manufacturing methods and that smaller does not always mean more precise. This issue is very important to many types of devices made using semiconductor manufacturing, particularly those having analog functionality including MEMS, NEMS, photonics, analog ICs, and nanotechnologies. It also is getting increased attention in digital ICs as the gate lengths have decreased. It is shown that the relative variations using these manufacturing methods are generally larger in magnitude compared to more conventional methods of production such as traditional machining operations. Moreover, since many of the devices made using semiconductor-based manufacturing methods have analog-functionality, device parameter variations can have a magnified impact on the variations exhibited in the device output behavior. Methods to estimate the impact of device parameter variations on the device output behavior are given, including an analytical method and Monte Carlo analysis. The impact of these variations on the manufacturing yield is explained and demonstrated. Lastly, a number of techniques that can be used to manage these device parameter variations so as to improve the manufacturing yield are given.

This paper reviews the recent advances in reaction-ion etching (RIE) for application in high-aspect-ratio microfabrication. High-aspect-ratio etching of materials used in micro- and nanofabrication has become a very important enabling technology particularly for bulk micromachining applications, but increasingly also for mainstream integrated circuit technology such as three-dimensional multi-functional systems integration. The characteristics of traditional RIE allow for high levels of anisotropy compared to competing technologies, which is important in microsystems device fabrication for a number of reasons, primarily because it allows the resultant device dimensions to be more accurately and precisely controlled. This directly leads to a reduction in development costs as well as improved production yields. Nevertheless, traditional RIE was limited to moderate etch depths (e.g., a few microns). More recent developments in newer RIE methods and equipment have enabled considerably deeper etches and higher aspect ratios compared to traditional RIE methods and have revolutionized bulk micromachining technologies. The most widely known of these technologies is called the inductively-coupled plasma (ICP) deep reactive ion etching (DRIE) and this has become a mainstay for development and production of silicon-based micro- and nano-machined devices. This paper will review deep high-aspect-ratio reactive ion etching technologies for silicon, fused silica (quartz), glass, silicon carbide, compound semiconductors and piezoelectric materials.

Chapter 6 reviews some of the important properties of the most commonly used materials in microsystems manufacturing. It is explained that the material properties are dependent on the processing conditions, and since many process sequences are customized, there is often insufficient knowledge of the properties during development. Most attention is given to two specific material properties, namely, Young’s modulus and residual stress, due to the fact that these usually have an important impact on the behavior of MEMS devices and the fact that these properties can vary quite significantly depending on the processing conditions. The use of test structures, including both mechanical and electrical, for measuring various material properties is explained. A review of the material properties for some of the most commonly used materials in microsystems manufacturing is then provided including semiconductors; dielectrics; and metals. The purpose of providing information about reported values of Young’s modulus and residual stress in deposited thin-film layers is to give an appreciation of the amount that these properties can vary with processing conditions and some guidance about the ranges that these properties may span.

Despite technological advancements and improved methodologies in forensic science and investigative practices, cold cases are a growing problem in the United States. Although there has been a surge in interest in solving cold cases due to advancements in technology, there has been very little research conducted on cold case investigation methodology. Many agencies lack the personnel and resources to devote adequate attention to cold cases. Federal dollars spent on cold case resolution in recent years focused only on those cases that could benefit due to improvements in DNA analysis techniques. The literature demonstrates that advances in other forensic disciplines can provide answers in unsolved crimes. In addition to inherent contributions to investigative invigoration and cold case resolution, collegiate cold case collaborations serve as a template for experiential and transformative illumination of unintended perceptual biases, investigative myopathy, and cognition fatigue. Such endeavors also provide practical insights into the sentinel importance of collaborator diversity, informed creativity, and objective analytics in both actively evolving and cold case investigations. This paper discusses the development of best practices guidelines for a cold case program in a collegiate setting.

This chapter covers the important topic process integration where a number of individual processing steps (covered in Chaps. 3 and 4 ) are combined into a process sequence for the implementation of MEMS devices. A general outline of yield improvement activities is given. Some of the challenges of process integration for MEMS are discussed including the significant time, cost, and risk that are commonly encountered. Integrated MEMS process sequences are defined as the merging of microelectronics onto the same substrate as the MEMS devices. Reasons why attempting to develop integrated MEMS is so difficult are also explained. Two notable examples of process technologies are reviewed; the first is a generic MEMS surface micromachining process sequence, and the second is an integrated MEMS process technology. Parameter variations that arise in process sequences are discussed, and an example of the parameter variations of a well-known MEMS process technology called PolyMUMPS™ is reviewed. The concept of design rules in microsystems manufacturing is then covered along with a review of the design rules for the PolyMUMPS™ process sequence. This chapter also briefly discusses the testing and packaging of MEMS, including device trimming and calibration.

A general overview of the processing steps commonly used in integrated circuit (IC) manufacturing is provided in Chap. 3. How each processing step is performed, the equipment commonly used, and guidance on the expected dimensional variations when performing the processing step are given. The subsequent chapter will focus on specialized processing steps used in MEMS fabrication. The major categories of processing steps used in IC fabrication include depositions or growths; lithography; etching; impurity doping; and metrology. Depending on the process sequence involved, there may also be other types of processing steps in the sequence as well such as planarization, rapid thermal anneals, and others. A number of these processing steps will be performed sequentially to implement the ICs, and some will be repeated multiple times. Once the fabrication is completed, the wafers will usually go through a series of tests to determine their functionality and performance. This is discussed in more detail in Chaps. 7, 8, and 9. Table 3.4 provides a compilation of the expected “best-case” dimensional variations for each of the processing steps reviewed in this chapter as a quick reference.

Chapter 2 provides a foundation for future chapters and begins with a review of the transduction mechanisms most commonly used in the implementation of MEMS microsensors and microactuators. Among the transduction effects covered includes piezoresistive; capacitive; piezoelectric; tunneling; magnetic; photoconduction; thermoelectric; electrostatic; thermal; shape-memory alloy; and others. The differences between a processing step; a process module; a process sequence; and a process technology are then described. The concept of batch fabrication is explained including the significant benefits that are derived from the use of this manufacturing method. Some of the important distinguishing characteristics of MEMS fabrication compared to IC manufacturing are reviewed, and reasons why MEMS is both more interesting and challenging compared to IC manufacturing are given. Specifically it is noted that MEMS design is very interesting since the number of device types and potential application areas is enormous. Nevertheless, MEMS implementation usually involves significant customization of both the design and the process sequence, and therefore the device designer often does not have much prior knowledge to leverage from. Lastly, a review of some of the basics about semiconductor materials, which are heavily used in MEMS manufacturing, is provided. Miller indices are explained as part of this discussion.

Microsystems fabrication utilizes a number of metrology techniques during development and manufacturing that are reviewed in Chap. 5. These techniques are used in development after processing steps are performed (reviewed in Chaps. 3 and 4) to find and diagnose problems that may be present. In manufacturing, metrology is employed to maintain quality control and thereby increase production yields. Metrology also enables the process engineers to monitor the status of the processing equipment used in production. There are a wide variety of metrology tools that are available, including inspection of the devices during and after fabrication; measurement of the dimensions of various important elements of the microsystems; and chemical analysis of materials used in fabrication. Some of the basic metrology techniques that have been developed for the IC industry are discussed, followed by a review of several more specialized metrology techniques specific for MEMS fabrication. Guidance as the accuracy of each of the metrology methods is given in Tables 5.2 through 5.5 providing a quick look-up summary of these metrology methods along with their resolution, precision, and accuracy.

This chapter covers the importance of ensuring quality and reviews methods for performing yield analysis in microsystems manufacturing. Methods for determining device functional and parametric yields are both reviewed. The types of defects that result in nonfunctional devices and various analytical techniques used for functional yield modeling based on point defects are explained. Parametric yield is then reviewed wherein a manufacturing function that incorporates all of the statistical distributions of the parameters describing the microsystems device’s output response is overlaid by an acceptance region to determine the yield. Methods to ensure quality during manufacturing using statistical process control (SPC) are covered. Control charts are used to show how processing steps can be monitored for whether they are in control or not. Process capability is shown to be an excellent gauge for whether a manufacturing process is able to produce devices having acceptable yields. Lastly, techniques for sampling of the measurements on wafers during and after manufacturing so as to obtain data that is rationally subgrouped so as to identify non-random changes are discussed.

The information covered from the previous chapters is brought together in this chapter to explain various techniques used in the microsystems design to manage the parameter variations resulting from use of microsystems manufacturing. Design for manufacturability (DfM) of microsystems is covered followed by some general recommendations for developing microsystems designs that adhere to DfM principles for MEMS devices. A review of the design techniques to manage device parameter variations is then provided including design centering: device parameter variation reduction; device size scaling; acceptance region increase; and best practices for layout. These techniques allow the variation region to be better aligned with the acceptance region. Each of these techniques is substantiated with examples in a one-dimensional parameter space, followed by how these techniques are used in multidimensional space. The use of Monte Carlo analysis techniques for design methods is then discussed including specific methods such as the centers of gravity algorithm; correlated sampling; and the common points method. The confidence of correct yield ranking is included in this discussion. Subsequently, sensitivity analysis for manufacturing or performance function improvement is outlined in both one- and multidimensional spaces. Lastly, a method for optimization of the manufacturing cost function is given.

This chapter focuses on a major theme of this volume, namely, how to analyze the variations in device parameters that occur when using microsystems fabrication technologies. It is explained that parameter variations are important since they result in the device output differing from the expected device output behavior that is based on the design. Two different types of parameter variations are discussed: systematic (bias) variations and random variations. Bias variations are fixed amounts of offsets that occur in the device parameters, while random parameter variations are caused by non-systematic process variations. It is discussed that the magnitude of these parameter variations can significantly vary depending on the specific details of the equipment, process being performed, and the aggressiveness of the device dimensions. This chapter also covers the important concepts of precision and accuracy. Both are important for a well-controlled manufacturing process. The tools of statistical analysis are covered for both continuous and discrete probability distributions. Various examples are used to reinforce how these statistical methods can be effectively employed in analyzing the variations of the device output behavior using microsystems manufacturing. The material covered in this chapter will be used in the next chapter in explaining parametric yield analysis.

This letter reports the research performed on the measurement of the repeatability of the resultant lateral dimensions across fused silica substrates that were etched using an inductively-coupled plasma reactive-ion etch process. We have developed and previously reported a highly-anisotropic plasma etch process with the demonstrated etch depths of over 100 microns deep into fused silica substrates and aspect ratios greater than 10 to 1. The across substrate repeatability of the lateral dimensions of the etched features is an extremely important parameter for any plasma etch process. The measured etched feature lateral dimensional repeatability for an average etch depth of 100 microns was found to be approximately 2.41% across each wafer over a total of 120 measurements taken. The capability to etch highly-anisotropic deep features with repeatable dimensional control into fused silica has important implications for a number of important MEMS applications. [2017-0088]

This paper reports research performed on comparing the etch mask selectivity of two different hard mask material layers, specifically nickel and copper, used for deep, anisotropic plasma etching of Silicon Carbide (SiC) substrates. Hard masks are required when performing deep etches into SiC given the extreme inertness of SiC combined with the high ion energies needed for the plasma etching of this material. Using a recently developed deep, highly-anisotropic inductively-coupled plasma process, we performed etches of SiC substrates with patterned hard masks composed of different types of materials to measure and compare their mask selectivity. The mask selectivity is important since it relates to how thick the hard mask layers must be in order to survive the required etch time to obtain a desired etch depth, and the thickness of the patterned hard mask layer has a direct impact on the resultant dimensional tolerances that can be obtained from the etch process. Using a deep, highly-anisotropic etch process we measured that the mask selectivity of nickel to be approximately 25 and that of copper to be 163. The capability to etch highly-anisotropic deep features into SiC using hard mask material layers has important implications for a number of applications in MEMS and microelectronics. (c) 2018 The Electrochemical Society.

This paper reports research performed on developing high rate of etch processes for the plasma etching of deep, highly anisotropic features into single-crystal 4H silicon carbide (SiC) substrates using an inductively coupled plasma process. To develop these etch processes, the authors conducted a design of experiments (DOE) whereby the most impactful etch process parameters were varied over predetermined values while the other etch process parameters were left unaffected. After performing an experimental etch on each sample, the samples were examined using various metrology methods to measure the etch outcomes. Using the investigational data accumulated during the DOE, the authors performed multiple regression analysis on this collected data in order to develop a model of the etch process that allows obtainment of desired outcomes, including a high etch rate, high mask selectivity, vertical sidewalls and minimal etch defects. Using optimized processes from the model, the authors were able to exhibit the ability to etch very deep features into SiC of more than 100 μm with nearly vertical sidewalls at high etch-rates. The capability to etch deep features at high etch rates into SiC is potentially useful for a number of microfabrication application areas.

Research conducted to develop Inductively-Coupled Plasma (ICP) etch processes is reported to allow the etching of deep, highly-anisotropic features into fused silica. To develop these etch processes, we conducted a Design of Experiments (DOE), whereby those parameters of the etch process having the most impact were varied over pre-defined values while leaving the other etch process settings unchanged. After each etch, the substrates were inspected to measure the results. Using the data collected, multiple regression analysis was conducted with the purpose of developing an accurate model of the process. This model was used to derive process parameter values to obtain the optimized etch results reported herein, including: an optimized recipe for attaining a maximum mask etch selectivity with etched features having vertical sidewalls (i.e., high anisotropy); and, an optimized recipe for maximum etch rate into fused silica with etched features having vertical sidewalls. Using the optimized recipes from the model developed, etching of very deep features (e.g., more than 100 microns) into fused silica with nearly vertical sidewalls was demonstrated. (c) 2017 The Electrochemical Society. All rights reserved.

This paper reports research performed on developing and optimizing a process recipe for the plasma etching of deep high-aspect ratio features into silicon carbide (SiC) material using an inductively-coupled plasma reactive-ion etch process. We performed a design of experiments (DOE) wherein the etch recipe parameters having the most impact on the etch process were varied over fixed ranges of predetermined values, while the other etch recipe process parameters were unchanged. Subsequently, the etched samples were analyzed so as to quantify the etch outcomes. Using the experimental data collected during the DOE, we then performed multiple regression analysis on this data to determine optimal etch tool parameters in order to achieve desired etch results. We have demonstrated the ability to etch very deep features into silicon carbide of more than 150 microns, having nearly vertical sidewalls and with aspect ratios of over 12 to 1 using the optimized etch process. The ability to fabricate deep high-aspect ratio features into SiC has important implications for a number of micro-electro-mechanical applications, particularly those involving harsh environments. The etch technology developments presented herein are applicable to SiC substrates and material layers in crystalline form, as well as to SiC in polycrystalline or amorphous forms.

This paper reports research performed on developing and optimizing a process recipe for the plasma etching of deep high-aspect ratio features into fused silica (fused quartz) material using an inductively coupled plasma reactive-ion etch process. As part of this effort, we performed a design of experiments (DOE), wherein the etch recipe parameters having the most impact on the etch process were varied over fixed ranges of predetermined values, while the other etch recipe process parameters were unchanged. Subsequently, the etched samples were analyzed so as to quantify the etch outcomes. Using the experimental data collected during the DOE, we then performed multiple regression analysis on this data to determine optimal etch tool parameters in order to achieve the desired etch results. Based on this work, we have demonstrated the ability to etch very deep features into fused silica of over 100 microns, having nearly vertical sidewalls, and with aspect ratios of over 10 to 1 using the optimized etch process. The ability to fabricate deep high-aspect ratio features into fused silica has important implications for a number of micro-electromechanical systems applications. The etch technology developments presented herein are applicable to fused silica, as well as to other silicon-dioxide-based materials including crystalline quartz.