In this paper we study the formation and behaviour of liquid Al-Ge alloy, its solidification, the resulting microstructures and the appearance of voids in bonded structure for MEMS packaging. The underneath layer influences the wettability of liquid Al-Ge as well as its solidification which can lead to undesirable Al dendrites. Each underneath layer imposes a critical value for the cooling rate above which dendrites are likely to appear. Blanket and patterned Al/Ge deposited wafers are bonded together with process parameters optimized thanks to previous results. The interfaces present a dendritic-free eutectic structure. Micro-voids are observed at the interfaces between Al and Ge phases. The Kirkendall effect and thermal stresses are two possible reasons for voiding phenomenon.

This paper presents a wafer-level fabrication process of 3D power module based on 8-inch wafer devices and 8-inch metallic bulk leadframe. This approach relies on the intermixing of the packaging process with the front-end fabrication of the power devices. The specific processes to obtain functional power devices and the metallic bulk leadframe manufacturing are described in the paper as essential key enablers of this packaging approach.

The Solar cell front side is a key design point for improved cell efficiency as a trade is made between optical losses (shadowing effect) and electrical losses (resistance). One solution consists in frontside contacts report to the cell's backside using through device conductive vias. By this way metal shadowing could be drastically reduced without increasing resistive losses. Such architecture is called Metal Wrap Through (MWT) and has been developed on silicon solar cells. Its application to III-V Multi-Junctions Solar Cells (MJSC) could be of great interest and has been simulated and studied for several years. We present here first functional MWT III-V dual-junction solar cells. Prototype developments have been based on inverted tandem solar cell (GaInP/GaAs) epitaxial structures grown on GaAs substrates. Front side contacts have been reported on the device's backside using specifically adapted Trough Semiconductor Via (TSV) technologies. Finally, the III-V active film was transferred on a conductive receiver by copper to copper (Cu//Cu) direct metal bonding. Morphological and chemical characterizations showed metallized and isolated contacts going through the tandem solar cell's structure. Electrical characterizations displayed many functional cells across 100mm wafers reaching efficiencies up to 26.3% @1 sun AM1.5d spectrum with a fill factor (FF) of 87.1%. Under concentration the efficiency raised up to 28.3% @167 suns. Beside these demonstrators, developed processes open ways to various possibilities such as large area III-V MJSC receivers.

Nous presentons dans ce papier l'etat d'avancement d'une approche d'assemblage collectif en 3D de modules electroniques de puissance, basee sur des etapes technologiques de fabrication a l'echelle de la plaque (200 mm de diametre dans notre cas). Le concept repose sur l'integration des etapes de packaging dans la fabrication front-end des composants. C'est une demarche globale de conception couplee composant-package. Cela inclut la conception des composants, les interconnexions, la fabrication et l'assemblage de toutes les parties. Les etapes specifiques de fabrication de composants fonctionnels ainsi que celles conduisant a la realisation d'un leadframe metallique sont decrites ici, comme des elements cles de l'approche de packaging collectif de modules de puissance.

Wafer level metal bonding involving copper layers is a key technology for three-dimensional integration. An appropriate surface activation can be performed in order to obtain room temperature direct bonding with bonding strength to be compatible with microelectronic device integration. In this paper, we focus on bonding strengthening mechanisms in the low temperature range from 20 to 100 °C. In order to improve the bonding interface closure, several process parameters are studied: water amount available when surfaces are brought into contact and copper layers deposition technique have been identified to be predominant in this low temperature range. Based on metal oxidation theory, several mechanisms are proposed and some calculations on this bonding strengthening are performed. For the first time, activation energies of this phenomenon are obtained for copper layers deposited by different method in the specific environment of the bonding interface. This study gives guidelines and recommendations for the integration of this metal bonding technique at low temperature.

In recent years, a great interest has emerged in the development of new wafer-scale assembly processes. Beside the mechanical strength required, some applications need a vertical conductivity leading to implement metal thin films as bonding layers. For its interesting properties in terms of resistivity and reliability, copper has been already used in metal-metal direct bonding configuration. Initially developed on amorphous silicon dioxide layers, the polycristallinity character of metal films has a direct impact on the direct bonding mechanisms. In this paper, we will study the effect of grain size on direct bonding of polycrystalline copper thin films. More specifically at temperature below 150°C, a fine-grain copper microstructure demonstrates a fast sealing strengthening. For higher temperature application, a larger grain size enables limiting the copper-barrier interface damage and preserves a strong mechanical link between substrates.

Promoted by the component miniaturization trend, three-dimensional integration appears as a promising option for implementation of the next generation of integrated circuits. In this context, copper is still an interesting material to be integrated to vertical interconnexion through direct metal-metal bonding processes. However, it was already reported that voiding phenomena occur in bonded copper layers for temperature beyond 300°C leading to serious reliability problems. This paper aims at explaining voiding mechanisms in the specific metal bonding configuration. Voiding characteristics are compared in different structures allows highlighting several thermal effects. It appears that the mechanical stress sustained by copper layers during post-bonding thermal processes is the main contribution in the voiding phenomenon. Creep mechanisms occurring in polycrystalline copper structure could be considered as the origin of this phenomenon. This study offers better understanding of reliability problems in structures involving encapsulated copper layers and can be used as guideline for metal bonding integration.

Copper–copper direct bonding is a fundamental procedure in three-dimensional integration. It has been reported that voiding occurs in bonded copper layers if process temperatures exceed 300°C; this leads to serious reliability issues. However, voiding nucleation and growth mechanisms have not been clearly established. Void characteristics were compared for different bonded structures specifically designed to identify the origin of void formation and its contribution. It seems that mechanical stress caused by different dilatation of silicon substrates and metal thin films leads to metallurgical creep. This stress-driven vacancy diffusion makes a major contribution to the reliability problem. This study provides better understanding of these physical phenomena and can be used as guideline for metal integration.

A photovoltaics conversion efficiency of 46% at 508 suns concentration was recently demonstrated with a four-junction solar cell consisting in a GaAs-based top tandem cell transferred onto an InP-based bottom tandem cell, by means of wafer bonding. We have successfully produced and characterized different InPOS (for InP-On-Substrate) composite substrates, that could advantageously replace fragile and expensive InP bulk wafers for the growth of the bottom tandem cell. The InPOS composite substrates include a thin top InP layer with thickness below 1 mu m, transferred onto a host substrate using the Smart Cut (TM) layer transfer technology. We developed InP-On-GaAs, InP-On-Ge and InP-On-Sapphire substrates with surface and crystal qualities similar to the InP bulk ones. A low electrical resistance of 1.4 m Omega.cm(2) was measured along the InP transferred layer and the bonding interface. An epitaxial bottom tandem cell was grown on an InPOS substrate, and the corresponding PL behavior was found identical to that of cells grown on InP bulk reference. The InP-based composite substrates are then very well suited for the fabrication of advanced devices like four-junction solar cells.

We report wafer level assembly of an advanced image sensor with control logic units and memories. The stack includes all back-end levels of a 0.13μm double damascene technology. The back-side imaging structure consists of 12 metal levels connected via direct hybrid copper-copper and oxide-oxide bonding. Thanks to a 3 step Chemical Mechanical Polishing (CMP) process applied at the bonding level and a proper wafer conditioning, the bonding was achieved at room temperature (RT) and under atmospheric pressure, with an x-y alignment precision below 400nm. The annealed structure has a pure copper metal connection with excellent mechanical and electrical properties. Beyond the next generation image sensors and hybrid integration, this demonstration appears as a good omen for a general three-dimensional (3D) IC integration via direct bonding.

Indium phosphide (InP) and gallium arsenide (GaAs) 100 mm wafers were bonded by direct wafer bonding in a cleanroom environment. Unexpected high bow values measured at room temperature after different thermal annealings are the focus of this study. Various experiments such as in situ bow measurements, surface XPS characterizations and TEM cross section observations highlight the key mechanisms that evolve with temperature. Over 200 °C, gallium oxide is formed at the bonded interface due to the presence of water that is trapped at the InP/GaAs interface during the hydrophilic bonding. These results allow us to explain the heterostructure debonding/re-bonding behavior.

In 3D integration industrial context, copper is widely favored over others metals as a bonding material for its exceptional electrical and mechanical properties. It has been already reported that directly bonded structures involving copper layers exhibit typical voids that drastically abound beyond 300 degrees C. In order to have a better understanding of the voiding process, we specifically designed structures involving materials and surfaces exhibiting different properties. These stacks underwent different bonding processes which mainly differ in the mechanical applied load. For each variation in this study the total volume of voids was estimated throughout a strict protocol. Thus, we demonstrate that voiding phenomena is related to a stress driven vacancy diffusion very comparable to standard metallurgical creep mechanisms. Regarding the origin of the vacancies, among all the possible options, two predominant sources have been identified. Better understanding of these physical phenomena should enable the achievement of advanced wafer assemblies exhibiting much higher reliability and quality.

This paper presents recent advances and breakthroughs of an alternative 3D packaging solution for vertical power devices. Direct bonding technology and trench isolation used for power device islanding are the cornerstone of this scheme of integration. Involving direct copper bonding layers, the technology is used during the mid-process to enable the wafer level bonding of vertical power devices to a joint metallic substrate while optimizing the devices intrinsic performances. Wafer level islanding and interconnect is used to simplify and guarantee the true 3D assembly at module level. This 3D assembly is based on the interconnect of matrices of low side and high side vertical power devices on top of each other. Our technology optimizes component surface height as well as alignments constraints. As a result, the true 3D integration of the active parts for power converters is optimized to the highest possible level, leading to strongly reduced EMI levels and increased switching speed capabilities. Key challenges, both on design, fabrication and implementation are presented, and the first prototypes based on four switching cells of vertical 500V power diodes and MOSFETs are introduced.

Wafer level metal bonding involving copper material is widely used to achieve 3D functional integration of ICs and ensure effective packaging sealing for various applications. In this paper we focus on thermocompression bonding technology where temperature and pressure are used in parallel to assist the bonding process. More specifically a broad range of conditions was explored and interesting results were observed and are reported. Indeed, despite a relatively high roughness, the presence of a native oxide and the lack of surface preparation, there still exists a process window where wafer level bonding is allowed. In these conditions, limiting the bonding mechanisms to basic copper diffusion is no longer satisfactory. In this study, a specific scenario inspired by both wafer bonding and metal welding state of the art is put forward. Accordingly, pure copper diffusion through the bonding interface is lined with plastic deformation and metallic oxide fracture. In addition, polycrystalline film deformation due to thermomechanical stress is highlighted and grain growth and voiding formation are observed and confirmed.

Direct metal bonding represents an advanced joining technology that allows vertical stacking with electrical conduction and even heat dissipation. For most metals used as bonding layers, direct bonding when operating at ambient air involves metal oxides. The bonding interface saddles with a trapped oxide layer that might affect electrical conduction and even complete sealing of bonding interface. Titanium especially, because of its high affinity with oxygen, makes oxide free direct bonding very difficult. In the mean time, the remarkable getter effect of Ti matrix allows the dissolution of oxygen during post bonding annealing. In this paper, the bonding limits with regards to the titanium thickness have been investigated. The key role of layer roughness on the bonding quality and energy has been pointed out. A titanium thickness below 10nm appears as a limit for an oxide free bonding.

Being able to model at what point a yield stress material starts to flow under its own weight is of great importance for many practical applications. However, describing the deformation of yield stress fluids under gravity is anything but a simple exercise due to the feedback between the shape of the deposited material and the locally acting stresses. In this article, we concentrate on a specific aspect of this problem: What is the maximum height of a pile of a yield stress fluid which can be obtained under gravity? For this purpose we use the example of liquid foams in which the yield stress is strongly coupled to the bubble size and the liquid fraction. We show that a good agreement between models and experiments is obtained over a wide parameter range in two limiting cases: When the yield stress is either higher or much lower than the normal stresses encountered in the material. (C) 2013 The Society of Rheology. [http://dx.doi.org/10.1122/1.4769826]