Area selective deposition (ASD) is a bottom-up process leading to a uniform deposition in only desired areas of a patterned substrate, avoiding the use of photolithography for patterning. However, whatever the strategy used to develop selective deposition by atomic layer deposition, there always comes a time when selectivity becomes defective and growth in undesired substrate areas must be corrected. This leads to the design of ASD by super-cycle alternating deposition and etch. Recent examples from the literature show a great diversity in the design of the etching step and indicate that the optimization of selective deposition by super-cycles is only possible through a careful optimization of the etching step parameters (chemistry, frequency, duration, etc.). In this paper, we discuss how to optimize this step and we show that different approaches can be developed to optimize the overall ASD process throughput, while simultaneously limiting process drift and contamination. We also show that complementary selective properties can prove a valuable leverage enabling ASD processes based on super-cycles, such as structure selective deposition, whereby a difference in thin film morphology in growth and non-growth areas can be smartly taken advantage of during the etching step.

3D and nanoscale dimensions make patterning extremely difficult to perform. In the past, patterning via plasma etching was a success thanks to the very good capacity of this process to etch one preferential material over the others: selective etching. Next step for advanced patterning will be to add a selective deposition step in addition to the etch one. Good examples are area selective deposition and topographical selective deposition. They will be discuss in this presentation

Atomic layer etching (ALE) of Ga-polar GaN (0001) using a standard inductively coupled plasma-reactive ion etching system is achieved in this work. The sequential process is using Cl2 to modify the surface in the adsorption step. For the activation step, the authors compare two rare gas plasmas, namely, Ar and Kr, and show a much larger and well-defined ALE window for the latter. The ALE of GaN is demonstrated by etching mesa structures masked with a photoresist. A constant etching rate per cycle of two monolayers is obtained. The experimental conditions of this self-limited process are found by changing both the adsorption and activation times, together with the source power. This provides an atomic-scale process for nanofabrication, with significant improvements to the GaN surface.

Desoxyribonucleic acid (DNA) origami architectures are a promising tool for ultimate lithography because of their ability to generate nanostructures with a minimum feature size down to 2 nm. In this paper, we developed a method for silicon (Si) nanopatterning to face up current limitations for high-resolution patterning with standard microelectronic processes. For the first time, a 2 nm-thick 2D DNA origami mask, with specific design composed of three different square holes (with a size of 10 and 20 nm), is used for positive pattern transfer into a Si substrate using a 15 nm-thick silicon dioxide (SiO2) layer as an intermediate hard mask. First, the origami mask is transferred onto the SiO2 underlayer, by an HF vapor-etching process. Then, the Si underlayer is etched using an HBr/O2 plasma. Each hole is transferred in the SiO2 layer and the 20 nm-sized holes are transferred into the final stack (Si). The resulting patterns exhibited a lateral resolution in the range of 20 nm and a depth of 40 nm. Patterns are fully characterized by atomic force microscopy, scanning electron microscopy, focused ion beam-transmission electron microscopy, and ellipsometry measurements.

In complementary metal oxide semiconductor (CMOS) technology, the integration of porous low-k materials becomes mandatory from the 45 nm technological node and beyond in order to reach interconnect performances. As previously described, such porous low-k materials can easily be damaged by all the process steps (especially etching and post-etch treatment processes) that can induce a potential increase in the dielectric constant. In this context, different hard mask strategies such as metallic or organic masks have been proposed for porous SiOCH patterning. Each integration scheme presenting advantages and drawbacks for porous SiOCH film integration is dealt with in this chapter.

For the fabrication of interconnect structures, porous low-k dielectrics are exposed to various plasma processes during etching, during post-etch treatments used to remove carbon-based masks and during treatment surfaces. We will describe here the main plasma processes used for the integration of low-k films, focusing on plasma surface interaction for methylsilsesquioxane (MSQ) films (porous and non-porous SiOCH). When not mentioned, the film is deposited by plasma enhanced chemical vapor deposition (PECVD).

The patterning of narrow trenches in porous SiOCH with a metallic hard mask can lead to the undulation of the dielectric lines between the trenches, also called wiggling. This phenomenon is attributed to the relaxation of the residual stress of the highly compressive hard mask by deforming the mechanically weak porous dielectric. This work analyses the parameters (titanium nitride stress and thickness, lines width and height, and materials Young modulus) potentially responsible for dielectric lines undulations using finite element mechanical modeling. These simulations are experimentally validated.

The best strategies to transfer nanoholes formed from the self-assembly of Polystyren/Polymethylmethacrylate (PS/PMMA) based block copolymers into a silicon substrate are investigated. The authors show that specific issues are associated with the plasma etching of materials through the PS masks obtained from self-assembly. Indeed, due to the nanometric size of sub-15 nm contact holes and to their inherently high aspect ratio (>5), plasma etching processes typically used to etch SiO2 and silicon in the microelectronic industry must be revisited. In particular, processes where the etching anisotropy relies on the formation of passivation layer on the feature's sidewalls are not adapted to nanometric dimensions because these layers tend to fill the holes leading to etch stop issues. At the same time, the ion bombarding energy must be increased as compared to a typical process to overcome differential charging effects in high aspect-ratio nanoholes. However, by developing appropriate processes—such as synchronized pulsed plasmas—the authors show that it is possible to etch 70 nm deep holes into silicon by using block copolymers and a hard mask strategy. Another interesting observation resulting from these experiments is that for sub-15 nm holes, a critical dimension (CD)-dispersion of few nm leads to strong aspect ratio dependent etch rates. In addition, a careful analysis of the dispersion of the holes' CD after each plasma steps shows that the CD control is far from satisfying advanced CMOS technology requirements. A critical issue comes from the uncompleted PMMA removal from the PS/PMMA matrix during our self-assembly process: variable amount of PMMA remains in the PS holes, leading to microloading effects during the etching steps, which in turn generates CD-control loss. This problem perhaps can be solved by combining UV exposure to acetic acid treatment to provide PS masks free of PMMA residues before plasma etching.

A comprehensive study on different polytypes (alpha-SiC and beta-SiC) and crystal orientations ((0001) and (11-20) of 6H-SiC) has been investigated in order to elaborate Silicon Carbide (SiC) nanopillars using inductively coupled plasma etching method. SiC nanopillars with cross section of rhombus, pentagon, and hexagonal have been obtained on beta-SiC (001), misoriented alpha-SiC (11-20), and alpha-SiC (0001) on-axis substrates, respectively. It has been found that crystal orientations and polytypes play key roles for the morphology of SiC nanopillars, which reflects the so-called Wulff's rule.

The integration of porous dielectric (low-k) in interconnects of integrated circuits is limited by the damage induced by plasma processes to the porous material. Plasma-damaged materials become hydrophilic, which degrades the electrical properties. However, the exact role of water is not fully understood. In this paper, the authors setup a dedicated cell to analyze water adsorption in plasma-damaged porous low-k dielectrics by infrared spectroscopy at various pressures of water vapor. The authors show that OH groups are present in the material under vacuum and that water adsorbs in the material first as icelike water and then as liquidlike water when the relative humidity is larger than similar to 50%. The consequences for microelectronics applications are discussed. (C) 2013 American Vacuum Society.

For the last ten years, the authors of this paper have been actively involved in studying the self-assembly of block copolymers for their high potential in nano-patterns fabrication. The aim of this paper is to give an overview of this important work by focusing on the main systems, process and results that have been obtained. In the first part of this paper, it will be shown that, a bi-layer and tri-layer strategies to transfer a diblock copolymer pattern into the subjacent substrate have been developed. As a result, a generic CMOS compatible lift-off strategy for transferring a block copolymer template to a semiconductor substrate is demonstrated. An aluminum oxide (Al2O3) hard mask is selectively deposited by atomic layer deposition in an organized array of holes obtained in a polystyrene (PS) matrix via polystyrene-b-poly(methyl methacrylate) (PS-b-PMMA) self-assembled layer. The Al2O3 nanodots act as a highly resistant mask to plasma etching, and are used to pattern high aspect ratio (> 10) silicon nanowires and nanopillars. Then, we report a synoptic methodology to optimize the long-range order induced by graphoepitaxy of block copolymer (BCP) self-assembly. Pre-patterned structures used in the graphoepitaxy approach have been generated by e-beam lithography on a commercial hydrogen silsquioxane resist. In a more prospective but promising approach, the second part of this paper focus on the study of the self-assembly of rod-coil amylose-b-polystyrene (Mal-b-PS) block copolymer. Interestingly, the nano-organization of this block copolymer falls in an interdomain spacing of about 10 nm, much smaller than flexible-flexible petrol block copolymer systems. In addition, hydrogen-bonding interactions between carbohydrate rods (amylose) and 40,4-bipyridine (bipy) molecules induce phase transitions. Such kind of systems coupled with the transferring approach and graphoepitaxy strategies exposed in this paper could permit to get ultra small (<10 nm) and well-organized patterns. 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim

Dense arrays of silicon and silicon germanium nanowires are fabricated using a top–down approach, which exploits the excellent patterning capabilities of inductively coupled plasmas. Using standard deep UV lithography on a previously deposited silicon oxide hard mask, silicon nanowires with straight and smooth sidewalls and a high aspect ratio greater than 60:1 can be obtained with SF6/O2/HBr/SiF4 plasma chemistries. The best results are obtained using Cl2/N2 high-density plasmas to pattern Si0.5Ge0.5 nanowires with an aspect ratio of 10:1.