The integration of new materials in the next generation of optoelectronic devices leads to several challenges. For instance, the etching of indium tin oxide (ITO, In2O3:Sn) faces the issue of the low volatility of In- and Sn-based etch products at room temperature. This is challenging for the etching process itself, but even more problematic when the inductively coupled plasma (ICP) reactor must be cleaned after etching: since the reactor walls are bombarded by low energy ions only, the removal of In- and Sn-based products redeposited on the walls can be very long and laborious. Therefore, we have investigated several plasma chemistries to find the most efficient reactor cleaning process suitable for ITO plasma etching. The results show that after ITO plasma etching the walls are indeed contaminated by indium. At the low temperature at which the reactor walls are regulated, BCl3/Cl-2 cleaning plasma is ineffective to remove this deposit while HBr and CH4/Cl-2 chemistries provide promising results.

Using CH3F/O-2/He based chemistries in high density plasmas for silicon nitride spacer etching, loss of silicon in active source/drain regions of CMOS transistors can be observed. Minimizing the so-called silicon recess during nitride spacer etching is extremely difficult to achieve but mandatory since it directly impacts the device performance. In this work, the authors investigated the benefits of CH3F/O-2/He/SiCl4 plasma to limit this recess. Using x-ray photoelectron spectroscopy, the mechanism for high Si3N4/Si selectivity is identified as the formation of a preferential thick SiOxFyClz passivation layer, generated at the silicon surface. The silicon damage is reduced by the growth of this thick layer, limiting the transfer of the reactive layer into the silicon film. These results have been confirmed on pattern structures for fully depleted silicon on insulator 14 nm technology showing the benefit of CH3F/O-2/He/SiCl4 etch plasma compared to CH3F/O-2/He plasma.

The fabrication of Si0.7Ge0.3 sub-10 nm nanochannels in gate-all-around devices requires a highly selective Si isotropic etching process. The etching of Si selectively to Si0.7Ge0.3 with CF4/N2/O2 downstream plasma has been investigated using various morphological and surface characterization techniques. Conditions such as 400 W microwave power, 700 mTorr pressure, 25 °C chuck temperature, and 22% CF4:22% N2:56% O2 feed gas mixture were found to be optimum for selectivity and etch rates. X-ray photoelectron spectroscopy showed that, during the etching process, a highly reactive 8 nm thick SiOxFy layer is formed on Si. Meanwhile, a 2 nm thick passivation layer is observed on SiGe. The latter is a mixture of SiOxFy and GeOxFy species that protected the alloy from etching. The process selectivity was improved by investigating different wet and dry oxidant treatments prior to etching. The dry oxidant treatment gives the best results in terms of selectivity. These results obtained on blanket wafers have been validated on pattern wafers. Scanning electron microscopy demonstrated that SiGe nanowires were fully released with a high selectivity after dry oxidation followed by the etching process.

Spacer etching in 3D CMOS technologies has become a very challenging step to be able to complete the etching while preserving channel and shallow trench insulation materials. The formation of parasitic spacers along fin sidewalls requires a lengthy overetch compared to conventional planar integrations to remove these undesired features, thereby drastically increasing the needed etching selectivities between silicon nitride, silicon (or SiGe), and silicon oxide. Based on an alternative etching chemistry, a new approach is assessed in this work, whose principle relies on selective passivation with an oxidelike material replacing the fluorine-containing organic layer encountered in dielectric etching with common fluorocarbons. Surface composition analyses demonstrate the preferential deposition on silicon with respect to silicon nitride yielding a high selectivity measured through etch rate tests on blanket films. The selectivity achieved is compatible with 3D CMOS spacer etching requirements. Despite the benefits shown by this alternative chemistry, some limitations prevent reaching the thorough elimination of parasitic spacer. A cyclic approach alternating selective passivation and nonselective etching is developed to overcome these limitations, which still provides effective silicon protection from etching. This cyclic sequence is evaluated on nanowire-type patterned structures and shows the complete removal of the parasitic spacer while providing a silicon loss of less than 2 nm. Work in development currently carries on to further improve this process and to fulfill all specifications for 3D CMOS spacer etching.

Full recess architecture for GaN based High Electron Mobility Transistor (HEMT) enables high mobility and high density of electrons to be conserved without compromising on voltage threshold. To obtain such architecture, standard RIE plasma etching processes are not suitable due to electrical degradation effects and to the lack of well controlled etch depth. To address these limitations, several Atomic Layer Etching (ALE) processes have been developed in the past. In this work, we study an atomic layer etching (ALE) of GaN based on cyclic steps composed of O-2 plasma followed by BCl3 plasma. XPS analysis of the GaN's top surface after each step of the O-2-BCl3 process enabled to propose an etching mechanism and to track nitrogen depletion. The cyclic process conserves the surface stoichiometry. Finally, this cyclic process has been validated on patterns, showing a good morphology, a good etch depth control and a slightly lower electrical degradation compared to standard RIE process.

Inductively coupled plasma (ICP) etching of Ge with high selectivity over Si and anisotropic etched profiles using CF4, HBr, SF6, and Cl2 reactive gases has been studied. Because pressure and biased power should be the most important parameters to drive selectivity and etch profile, they were varied from 4 to 50 mTorr and from 0 to 50 W, respectively, so as to investigate their influence on process. Total gas flow (100 sccm) and source power (350 W) were initially held constant. Selectivity greater than 100:1 of Ge over Si was achieved using 100 % Cl2 etch gas at 50 mTorr and zero bias power but the profile of the etched features was isotropic. With the addition of N2 to the feed gas (Cl2) the profile became more anisotropic. A three steps ICP etch process was developed with a final Ge/Si etch selectivity of 5:1 and anisotropic profiles.

An optimized Ge-rich GeSbTe (GST) ternary alloy is investigated to improve the thermal stability of future phase change memories (PCMs). The patterning process used for their manufacturing may change the GST surface chemical composition, thus damaging the devices performances. The impact of HBr plasma etching, O-2 plasma stripping and HF cleaning is evaluated. Etching induces a Te enrichment at the surface. Stripping has the strongest influence creating a GST oxide at the surface, mainly composed of GeO2. This thin layer is removed by HF cleaning thus revealing the underlying Te-rich GST phase. Oxidation during long-term air exposure is also investigated. After etching (or cleaning), oxygen saturation is reached after 30 days of air exposure. The surface of GST just after stripping is also oxygen saturated, with no more evolution under air exposure.

Directed self-assembly of block copolymers is one of the most promising solutions to reach sub-20 nm patterns. A critical challenge of this technique is the PMMA removal selectively to polystyrene (PS). A very high PMMA:PS selectivity (>10:1) is required to conserve a sufficient PS pattern thickness allowing pattern transfer to sublayers. In this paper, the authors propose a CH4-N2 chemistry allowing a full PMMA removal without PS consumption. This chemistry is based on controlling the polymerization rate by tuning the ratio between methane and di-nitrogen. Finally, the benefits of this etch chemistry have been validated on PS-b-PMMA with a lamellar configuration.

Chalcogenide materials based on GeSbTe (GST) ternary alloys are patterned using inductively coupled plasma in the manufacturing of phase change memories. The current process challenge is to maintain the GST composition and surface morphology to guarantee the memory performances. In this paper, the authors investigate the etching effects of different halogen plasmas (HBr, CF4, and Cl2) on an optimized Ge-rich GST alloy. Using x-ray photoelectron spectroscopy (XPS) and plasma profiling time-of-flight mass spectrometry as complementary techniques, the authors noticed that the etched GST surface shows a stronger Te-rich damaged layer in the sequence of CF4 > Cl2 > HBr. It is closely related to the higher affinity between halogen and GST elements in the sequence of Ge > Sb > Te. By comparing the etch rates with and without rf bias voltage, HBr etching is shown to be mainly related to the physical ion bombardment. On the contrary, Cl2 plasma is mostly chemical and generates the roughest surface. The presence of a C-F passivation layer with CF4 plasma shows that both chemical reactivity and physical bombardment are necessary to etch efficiently the GST film. The oxidation of the HBr-etched GST surface was monitored by XPS as a function of several air exposure times. As a conclusion, the GST oxidation becomes critical after 24 h of air exposure.

In this paper we analyze recent progress in Phase-Change Memory (PCM) technology targeting both Storage Class Memory and embedded applications. The challenge to achieve a high temperature data retention without compromising the device programming speed can be addressed by material engineering. We show that volume and thermal confinement improvement of the phase-change material enables a high (10-fold) reduction of the programming current, achieved also by the optimization of the device architecture, in particular in the case of a confined structure. It leads to a higher cell efficiency proven by a 6x reduction of the programming current density wrt a standard PCM structure. Furthermore, we demonstrate the reduction of thermal losses by the tuning of the thermal conductivity of the dielectrics surrounding the phase-change material. Finally, we propose some considerations about the PCM ultimate scaling and the reliability at such dimensions, showing that the engineering of the bottom electrode/phase-change material interface can lead to a reduced variability in scaled devices.

A critical challenge for directed self-assembly of block copolymers is the selectivity between the two polymer phases. Polystyrene-block-poly(methyl methacrylate) (PS-b-PMMA) is one of the most studied block-copolymers to reach sub-20 nm patterns. A very high PMMA/PS selectivity (>10:1) is required to conserve a sufficient PS pattern thickness allowing pattern transfer to sublayers. In this paper, the authors propose to develop a chemistry allowing a full PMMA removal without PS consumption. It is based on CO and CO-H2 cycles allowing to get a very high etch control. The proposed etch mechanisms have been understood thanks to x-ray photoelectron spectroscopy analyses performed on blanket wafers. Finally, this new etch process has been validated on the cylindrical PS-b-PMMA patterned structure.

Spacer etching realization is considered today as one of the most critical processes for the fully depleted silicon on insulator devices realization. The challenge arises from the fact that low-k spacer needs to be introduced to improve device performances. In this paper, a new approach to etch the low-k SiCO film was investigated. This approach is based on the SiCO film modification by H2 plasma followed by a removal step of this modified layer using hydrofluoric acid- (HF) based wet cleaning. It has been demonstrated that SiCO layer modification depth is controlled by plasma parameters like bias voltage. The SiCO film modification induced by H2 plasma has been well understood by x-ray photoelectron spectroscopy, infrared spectroscopy analyses in transmission or in multi-internal reflection. It has been demonstrated that the H2 plasma exposure converts the SiCO film in volume into an SiOxHy film, explaining the higher damaged film removal rate when dipped in liquid phase HF. Finally, the compatibility of the new etch approach with the SiCO low-k film has been demonstrated on pattern structures.

Recent developments in CMOS devices such as FinFET, FDSOI or stacked nanowire FETs (SNWFETs) have led the industry to consider increasingly complex integration processes while aiming at smaller and smaller devices. This paper proposes new concepts of device integration based on the use of hydrogen silsesquioxane (HSQ). Recently employed to replace polysilicon sacrificial gate in gate last processes, its use could also be extended for building the whole transistor level including device lateral insulation, multi-workfonction layouts, self-aligned contacts and possibly the first layer of metal interconnects. If several EUV masks could be employed for such a use, HSQ patterning once enhanced by multi-electron beam lithography, could allow to perform all these features within a single exposure step without involving any conventional etching or stripping steps.

With transistors size scaling down, device processing requirements become more and more stringent. For technology node beyond 14 nm, one of the most critical step is the spacer etching. It requires a perfect anisotropy (no CD loss) without damaging nor consumption of the exposed material like silicon, silicon germanium and oxide [1,2]. In planar transistor, the silicon or silicon germanium consumption is limited by the short over-etch process (30-50%). However for 3D devices, the silicon fin is directly exposed during the removal of the silicon nitride on the active area sidewalls. This is the major issue since in this case, important over etch is required (>200%) to fully remove the residues at the bottom of the fin. Therefore, the spacer etch is considered today as one of the most challenging etch process for 2D but more especially 3D devices. In this paper we propose to compare conventional etch process to new approaches to reach the stringent etch requirements for 2D and 3D devices. The first part of this study focuses on the characterization of CH2F2/O2/He/CH4 plasma performed in an Inductively-Coupled Plasma (ICP) etch tool. It was shown that playing on different parameters (bias, reagent, bias pulsing…) the maximum selectivity to silicon reached 13.5. In our experimental conditions, the lower Si consumption is estimated to 0.6 nm and 3 nm for 2D and 3D device applications. Whatever the operating plasma conditions, XPS analyses shown that selectivity to silicon has been explained by an oxide formation at the top of the silicon layer. A second part of the study will focus on an original approach for planar transistor application [3]. This approach consists in light ion implantation of hydrogen in the silicon nitride layer (in an inductively or capacitively-coupled plasma reactor), and then in a second step, in a highly selective removal process based on gaseous hydrofluoric acid (HF). Film modification and reaction with removal process have been understood thanks to XPS and infrared spectroscopy. In this part, the implanted material has been characterized and the chemical reactions with gaseous HF have been investigated. It has been pointed out that implantation proceeds by increasing the H bonding with N and Si atoms which allowed the selective reaction of gaseous HF with the damaged thickness by forming an hexafluorosilicate salt. This salt was then easily removable in an aqueous solution showing a clean surface after treatment. It has also been demonstrated that playing on the gaseous HF concentration inside the chamber improved the selectivity to non-implanted SiN and silicon dioxide up to 31 and 39 respectively. This method has been turned out to be an accurate method to etch silicon nitride with a nearly atomistic precision. A third part discusses about the spacer etching for 3D devices like FinFET or stacked nanowires. In this part, due to the complex architecture of patterns, the implantation has been performed thanks to ion implantation and a tilted angle has been used to target specific silicon nitride areas to remove. It will be shown that argon ion is the most suitable implant element for a fast etch of implanted SiN on blanket wafers and test are ongoing on pattern samples to validate the technique. [1] B. E. E. Kastenmeier, P. J. Matsuo, and G. S. Oehrlein, J. Vac. Sci. Technol. A 17 (6), 3179 (1999). [2] K. Eriguchi, Y. Nakakubo, A. Matsuda, Y. Katao, K. Ono, IEEE Electr. Device L. 30 (7), 712 (2009). [3] N. Posseme, O. Pollet, and S. Barnola, J. Appl. Phys. 105, 051605 (2014).

Through three collaborative R&D programs, IDEAL for Directed Self-Assembly Lithography, IMAGINE for Massively Parallel Electron Beam Lithography and INSPIRE for NanoImprint Lithography, CEA-LETI is currently assessing and boosting the development of these alternative technologies through strategic partnerships and innovative mix of them. This paper will present the latest process developments achieved on both chemically and non-Chemically Amplified Resist exposed with a low accelerating voltage (5 kV) exposure platform developed by Mapper Lithography. Several approaches will be presented to manage the Resolution-Sensitivity-Line Width Roughness challenge as well as the etching transfer in the underneath stacks required at the 28 nm node. For the Directed Self-Assembly (DSA) of Block Copolymers (BCP) patterning solution, even if it is considered as a promising patterning solutions due to its simplicity, low cost of processing and capability to generate high density patterns, some challenges (DSA-friendly design, low defectivity and accurate placement error) still need to be addressed for a complete adoption of DSA in manufacturing. We propose to discuss the advanced integration flows using DSA of block copolymer for PS-PMMA materials, like "DSA planarization" approach and also surface guide affinity tuning. Then, NIL wafer scale technology will be assessed thought CDU and printed resist feature height measurements. These result will underline the key process parameters that will define the integration scheme of such technology in high volume manufacturing. This paper will also highlight the specific metrology requirements and method needed to properly evaluate such patterning technology.

Silicon nitride spacer etching is one of the most critical step for the fabrication of CMOS transistors in microelectronics. It is usually done by plasma etching using a fluorocarbon based chemistry. However, from the 14 nm technology node and beyond, this etching process no longer allows the etch specifications to be reached (nonformation of a foot, poor critical dimension control below 1 nm). To overcome this issue, a new process was developed. It consists of two steps: in a first step, the silicon nitride film is modified by light ion implantation (hydrogen), and then followed by a removal step of this modified film by hydrofluoric acid (HF). In this paper, the authors propose to remove the implanted/modified silicon nitride using gaseous HF and understand the associated etching mechanisms using infrared spectroscopy and x-ray photoelectron spectroscopy at different stages of the process sequence (after implantation/modification, gaseous HF process, and post-treatment).