Full-scale quantum computers require the integration of millions of quantum bits. The promise of leveraging industrial semiconductor manufacturing to meet this requirement has fueled the pursuit of quantum computing in silicon quantum dots. However, to date, their fabrication has relied on electron-beam lithography and, with few exceptions, on academic style lift-off processes. Although these fabrication techniques offer process flexibility, they suffer from low yield and poor uniformity. An important question is whether the processing conditions developed in the manufacturing fab environment to enable high yield, throughput, and uniformity of transistors are suitable for quantum dot arrays and do not compromise the delicate qubit properties. Here, we demonstrate quantum dots hosted at a 28Si/28SiO2 interface, fabricated in a 300 mm semiconductor manufacturing facility using all-optical lithography and fully industrial processing. As a result, we achieve nanoscale gate patterns with remarkable homogeneity. The quantum dots are well-behaved in the multi-electron regime, with excellent tunnel barrier control, a crucial feature for fault-tolerant two-qubit gates. Single-spin qubit operation using magnetic resonance reveals relaxation times of over 1 s at 1 Tesla and coherence times of over 3 ms, matching the quality of silicon spin qubits reported to date. The feasibility of high-quality qubits made with fully-industrial techniques strongly enhances the prospects of a large-scale quantum computer

One of the main bottlenecks in the pursuit of a large-scale--chip-based quantum computer is the large number of control signals needed to operate qubit systems. As system sizes scale up, the number of terminals required to connect to off-chip control electronics quickly becomes unmanageable. Here, we discuss a quantum-dot spin-qubit architecture that integrates on-chip control electronics, allowing for a significant reduction in the number of signal connections at the chip boundary. By arranging the qubits in a two-dimensional (2D) array with $\sim$12 $\mu$m pitch, we create space to implement locally integrated sample-and-hold circuits. This allows to offset the inhomogeneities in the potential landscape across the array and to globally share the majority of the control signals for qubit operations. We make use of advanced circuit modeling software to go beyond conceptual drawings of the component layout, to assess the feasibility of the scheme through a concrete floor plan, including estimates of footprints for quantum and classical electronics, as well as routing of signal lines across the chip using different interconnect layers. We make use of local demultiplexing circuits to achieve an efficient signal-connection scaling leading to a Rent's exponent as low as $p = 0.43$. Furthermore, we use available data from state-of-the-art spin qubit and microelectronics technology development, as well as circuit models and simulations, to estimate the operation frequencies and power consumption of a million-qubit processor. This work presents a novel and complementary approach to previously proposed architectures, focusing on a feasible scheme to integrating quantum and classical hardware, and significantly closing the gap towards a fully CMOS-compatible quantum computer implementation.

Multilayer stack height in 3DNAND has reached the limit of the aspect ratio that etch technologies can cost-effectively achieve. The solution to achieve further bit density scaling is to build the stack in two tiers, each etched separately. While lowering the requirements on etch aspect ratio, stacking two tiers introduces a critical overlay at the interface between the stacks. Due to the height of each stack, stress- or etch-induced tilt in the channel holes is translated into overlay. Characterizing and controlling the resulting complex overlay fingerprints requires dense and frequent overlay metrology. The familiar electron beam metrology after etch-back (DECAP) is destructive and therefore too slow and expensive for frequent measurements. This paper will introduce a fast, accurate & robust data-driven method for In Device Overlay Metrology (IDM) on etched 3DNAND devices by making use of specially designed recipe setup targets. Also, potential applications for process control improvement will be demonstrated.

We study spatial noise correlations in a Si/SiGe two-qubit device with integrated micromagnets. Our method relies on the concept of decoherence-free subspaces, whereby we measure the coherence time for two different Bell states, designed to be sensitive only to either correlated or anti-correlated noise respectively. From these measurements, we find weak correlations in low-frequency noise acting on the two qubits, while no correlations could be detected in high-frequency noise. A theoretical model and numerical simulations give further insight into the additive effect of multiple independent (anti-)correlated noise sources with an asymmetric effect on the two qubits. Such a scenario is plausible given the data and our understanding of the physics of this system. This work is highly relevant for the design of optimized quantum error correction codes for spin qubits in quantum dot arrays, as well as for optimizing the design of future quantum dot arrays.

Electrons and holes confined in quantum dots define excellent building blocks for quantum emergence, simulation, and computation. Silicon and germanium are compatible with standard semiconductor manufacturing and contain stable isotopes with zero nuclear spin, thereby serving as excellent hosts for spins with long quantum coherence. Here, we demonstrate quantum dot arrays in a silicon metal-oxide-semiconductor (SiMOS), strained silicon (Si/SiGe), and strained germanium (Ge/SiGe). We fabricate using a multi-layer technique to achieve tightly confined quantum dots and compare integration processes. While SiMOS can benefit from a larger temperature budget and Ge/SiGe can make an Ohmic contact to metals, the overlapping gate structure to define the quantum dots can be based on a nearly identical integration. We realize charge sensing in each platform, for the first time in Ge/SiGe, and demonstrate fully functional linear and two-dimensional arrays where all quantum dots can be depleted to the last charge state. In Si/SiGe, we tune a quintuple quantum dot using the N + 1 method to simultaneously reach the few electron regime for each quantum dot. We compare capacitive crosstalk and find it to be the smallest in SiMOS, relevant for the tuning of quantum dot arrays. We put these results into perspective for quantum technology and identify industrial qubits, hybrid technology, automated tuning, and two-dimensional qubit arrays as four key trajectories that, when combined, enable fault-tolerant quantum computation.

We investigate the structural and quantum transport properties of isotopically enriched Si/SiO2 stacks deposited on 300-mm Si wafers in an industrial CMOS fab. Highly uniform films are obtained with an isotopic purity greater than 99.92%. Hall-bar transistors with an oxide stack comprising 10 nm of SiO2 and 17 nm of Al2O3 (equivalent oxide thickness of 17 nm) are fabricated in an academic cleanroom. A critical density for conduction of 1.75 × 1011 cm−2 and a peak mobility of 9800 cm2/Vs are measured at a temperature of 1.7 K. The Si/SiO2 interface is characterized by a roughness of = 0.4 nm and a correlation length of = 3.4 nm. An upper bound for valley splitting energy of 480 μeV is estimated at an effective electric field of 9.5 MV/m. These results support the use of wafer-scale Si/SiO2 as a promising material platform to manufacture industrial spin qubits.

Current implementations of quantum computers suffer from large numbers of control lines per qubit, becoming unmanageable with system scale up.Here, we discuss a sparse spin-qubit architecture featuring integrated control electronics significantly reducing the off-chip wire count.This quantumclassical hardware integration closes the feasibility gap towards a CMOS quantum computer.

The pursuit of quantum computing in silicon is motivated by the facts that (1) Si can be isotopically engineered into a nuclear-spin-free material, yielding long spin lifetimes, and (2) CMOS fabrication technology can be leveraged for manufacturing qubits in the large numbers required for fault-tolerant quantum computing. Establishing wafer-scale ${}^{28}$Si has been seen as a major bottleneck, but here the authors integrate the isotope into a state-of-the-art CMOS fab. The quantum transport properties of the two-dimensional electron gas obtained at the ${}^{28}$Si/${}^{28}$SiO${}_{2}$ interface support the use of wafer-scale ${}^{28}$Si as a material platform for industrial spin qubits.

We investigate the structural and quantum transport properties of isotopically enriched Si-28/(SiO2)-Si-28 stacks deposited on 300-mm Si wafers in an industrial CMOS fab. Highly uniform films are obtained with an isotopic purity greater than 99.92%. Hall-bar transistors with an oxide stack comprising 10 nm of (SiO2)-Si-28 and 17 nmof Al2O3 (equivalent oxide thickness of 17 nm) are fabricated in an academic cleanroom. A critical density for conduction of 1.75 x 10(11) cm(-2) and a peak mobility of 9800 cm(2)/Vs are measured at a temperature of 1.7 K. The Si-28/(SiO2)-Si-28 interface is characterized by a roughness of Delta = 0.4 nm and a correlation length of Lambda = 3.4 nm. An upper bound for valley splitting energy of 480 mu eV is estimated at an effective electric field of 9.5 MV/m. These results support the use of wafer-scale Si-28/(SiO2)-Si-28 as a promising material platform to manufacture industrial spin qubits.

Quantum computing's value proposition of an exponential speedup in computing power for certain applications has propelled a vast array of research across the globe. While several different physical implementations of device level qubits are being investigated, semiconductor spin qubits have many similarities to scaled transistors. In this article, we discuss the device/integration of full 300mm based spin qubit devices. This includes the development of (i) a 28 Si epitaxial module ecosystem for growing isotopically pure substrates with among the best Hall mobility at these oxide thicknesses, (ii) a custom 300mm qubit testchip and integration/device line, and (iii) a novel dual nested gate integration process for creating quantum dots.

We investigate the magnetic field and temperature dependence of the single-electron spin lifetime in silicon quantum dots and find a lifetime of 2.8 ms at a temperature of 1.1 K. We develop a model based on spin-valley mixing and find that Johnson noise and two-phonon processes limit relaxation at low and high temperature, respectively. We also investigate the effect of temperature on charge noise and find a linear dependence up to 4 K. These results contribute to the understanding of relaxation in silicon quantum dots and are promising for qubit operation at elevated temperatures.

We investigate the structural and quantum transport properties of isotopically enriched ^28Si/^28SiO_2 stacks deposited on 300 mm Si wafers in an industrial CMOS fab. Highly uniform films are obtained with an isotopic purity greater than 99.92%. Hall-bar transistors with an equivalent oxide thickness of 17 nm are fabricated in an academic cleanroom. A critical density for conduction of 1.75×10^11 cm^-2 and a peak mobility of 9800 cm^2/Vs are measured at a temperature of 1.7 K. The ^28Si/^28SiO_2 interface is characterized by a roughness of Δ=0.4 nm and a correlation length of Λ=3.4 nm. An upper bound for valley splitting energy of 480 μeV is estimated at an effective electric field of 9.5 MV/m. These results support the use of wafer-scale ^28Si/^28SiO_2 as a promising material platform to manufacture industrial spin qubits.

Enrichment of the spin-zero $^{28}$Si isotope drastically reduces spin-bath decoherence in silicon and has enabled solid state spin qubits with extremely long coherence and high control fidelity. The limited availability of isotopically enriched $^{28}$Si in industrially adopted forms, however, is a major bottleneck to leverage CMOS technology for manufacturing qubits with the quality and in the large numbers required for fault tolerant quantum computation. Here we show wafer-scale epitaxial growth of isotopically enriched $^{28}$Si/$^{28}$SiO$_2$ stacks in an industrial CMOS fab, and demonstrate highly uniform films with an isotopic purity greater than $99.92\%$. We induce a two dimensional electron gas, the cornerstone of silicon spin qubit architectures, at the isotopically enriched semiconductor/oxide interface by electrical gating. To confirm the high quality growth, we perform electrical probing and show matching properties for fin transistors in $^{28}$Si and natural Si, fabricated using the same high volume manufacturing process. Quantum transport measurements at cryogenic temperature validate wafer-scale $^{28}$Si as a suitable material to host qubits. The establishment of an industrial supply of isotopically enriched Si, previously thought to be a major hurdle, provides the foundation for high volume manufacturing of long-lived spin qubits.

Quantum computing holds the promise of exponential speedup compared to classical computing for select algorithms and applications. Relatively small numbers of logical quantum bits or qubits could outperform the largest of supercomputers. Quantum dots in Si-based heterostructures and superconducting Josephson junctions are just two of the many approaches to construct the qubit. These, in particular, bear similarities to the transistors and interconnects used in advanced semiconductor manufacturing. While initial results on few-qubit systems are promising, advanced process control is expected to improve the qubit uniformity, coherence time, and gate fidelity needed for larger systems. This can be realized through the systematic characterization of film growth, interface control, and patterning.